摘要
介绍了一种应用于低中频GPS接收机的CMOS可编程放大器.该放大器通过采用基于差分对简并电路的线性化技术,实现了以6dB为步长的96dB数控增益范围,同时利用工作在亚域值区工作的晶体管代替电阻用于直流偏移校正模块当中有效地节约了芯片面积,仿真结果表明其带宽为300MHz,最大增益时其噪声指数为23.7dB,ⅡP3在最低增益时达到-5dBm,全局增益误差为0.03dB.设计采用了0.18μmCMOS数模混合工艺库实现,面积约为0.097mm2,在1.8V供电电压下,功耗为6.3mW.
A programmable gain amplifier （PGA） is designed for a Low-IF GPS receiver. Linearity method which was based on the differential degeneration and grn boost structure was used in the circuit. Transistors which are working in the sub-threshold region are applied in the built-in De-Offset correction circuit. This PGA provides a 96-dB digitally controlled gain range with a step of 6-dB, and the overall gain accuracy is 0.03dB. The bandwidth of the PGA is 300MHz. The noise figure at the maximum gain is 23.7dB. The IIP3 is - 5dBm for the minimum gain. The PGA is implemented in a 0.18μm CMOS process and approximately occupies 0. 097mm^2. This PGA consumes 3.5mA at a 1.8V supply.
出处
《微电子学与计算机》
CSCD
北大核心
2008年第12期103-105,共3页
Microelectronics & Computer
基金
中国科学院创新基金项目
