摘要
DFT伪码捕获算法在进行伪码搜索的同时估计多普勒频偏,为了满足捕获精度要求,需要增加DFT点数,但随着运算点数的增加硬件实现难度成倍增长。本文提出一种基于FPGA的在不增加DFT点数的前提下实现高精度伪码捕获的方法,详细介绍了如何通过采用查找表和浮动窗等方法在保证系统性能的同时节省资源,通过在FPGA器件中验证表明该方法捕获速度快,精度高,硬件实现简单,占用资源少,有很强的实用价值。
DFT-Code acquisition method can estimate Doppler shifts while searching PN phase. It is necessary to increase the num- ber of DFT points to keep the frequency error in the range of trace loop. However, it is impossible to implement DFT algorithm on FPGA when the number of points is big, This paper introduces a method on FPGA in details which can keep the accuracy of frequency estimation but not increase the number of DFT points. The test results of implementation on FPGA shows the method can reduce the acquisition time and save resources while keeping good accuracy of frequency estimation.
出处
《微计算机信息》
北大核心
2008年第21期118-119,141,共3页
Control & Automation
关键词
扩频信号
捕获
DFT
多普勒频偏
频率估计
Spread spectrum signal
Acquisition
DFT
Doppler shift
frequency estimation
