摘要
在研究了IEEE1149.1标准和SOPC技术的基础上,提出了基于FPGA的边界扫描总线控制系统的设计;使用VHDL语言,在FPGA中将传统的边界扫描总线控制器的功能以IP Core的形式实现,并与NiosII处理器共同构成嵌入式边界扫描总线控制系统;经仿真验证,该系统产生的测试信号完全满足IEEE1149.1标准协议的要求;该系统具有较强的集成度、灵活性和可定制性,能够应用于IC或PCB的边界扫描测试以及相关的研究和实验。
According to the study of the IEEE1149. 1 and the SOPC technology, the design for embedded BS bus control system based on FPGA has been put forward. By means of VHDL, the traditional BS bus controller＇s functions have been implemented with the form of iP core in the FPGA , then both of the IP core and a NiosII processor have made up of the embedded BS bus control system. This system＇s test signals fulfill the IEEE1149. protocol, which has been proved by the simulation. The system is integrated into a FPGA, so it is more integration, agility and customizable. It can be used in the boundary scan test of IC and PCB , as well as in the research and experiment of the technology widely.
出处
《计算机测量与控制》
CSCD
2008年第2期159-162,共4页
Computer Measurement &Control
