摘要
为满足SoC中JPEG静止图像实时解压缩要求,在完成JPEG解码器C语言建模的基础上,采用自顶向下的设计方法,完成了JPEG Baseline解码器设计,并在FPGA开发板上验证了设计结果。该设计与ACTEL、4I2I等公司的IP核相比具有相近的解压缩速度,能满足实时解码要求。
In order to meet the real-time decoding of JPEG on SoC, based on the C language JPEG decoder model ,this design realizes the JPEG baseline decoder with the method ＂Top-Down＂ ,and the result is tested on the FPAG board. Compared with the JPEG IP CORE from the ACTEL ,4I2I corporations ,this design has the close result and meets the real-time requirement.
出处
《电子技术应用》
北大核心
2008年第2期45-47,51,共4页
Application of Electronic Technique
