摘要
文章采用萨方程对CMOS工艺的6管静态存储单元结构进行分析计算,探讨了在工艺特征尺寸确定的情况下,晶体管沟道宽度为何值时存储阵列的数据输出延迟最小的估算方法;利用Matlab求解得到一个非线性方程;该方法适用于不同的存储阵列和特征尺寸,可以快速地估算出晶体管沟道宽度,为设计存储器单元版图时提供了方便。
This paper deals with the six-transistor static random access memory（SRAM） cell in CMOS technology by Sah＇s equation. In the case that the feature size is fixed, an estimation method for ascertaining the channel width is presented in order to minimize the delay of data output of the storage array. An obtained nonlinear equation is solved by using Matlab. This estimation method,by which the channel width of transistors can be evaluated rapidly, is suitable for diverse storage arrays and feature sizes, and it provides much convenience for layout engineers.
出处
《合肥工业大学学报（自然科学版）》
CAS
CSCD
北大核心
2007年第9期1215-1218,共4页
Journal of Hefei University of Technology：Natural Science
基金
中国兵器工业部214所资助项目(bj2411b)
