摘要
差错控制是数据通信中常用的传输错误检测措施。接收端通过对接收到的数据进行循环冗余校验(CRC),就可以检测出数据包在传输过程中是否发生损坏。本文详细介绍CRC的基本原理、USB协议中的CRC算法及其VHDL实现。与传统的软件编程实现相比,采用VHDL实现具有更高速度和可靠性,而且可以很方便地嵌入到应用系统中,具有广泛的应用前景。
Error-correction is more popular used to check error in data communication. It can detect whether packet has been corrupted during transport by cyclic redundancy check. The principle and algorithm of cyclic redundancy check used in USB is presented. Implementation of CRC based on VHDL not only has more reliability but also can be easily embedded in application system.
出处
《微计算机信息》
北大核心
2007年第05Z期289-290,277,共3页
Control & Automation
基金
陕西省教育厅(04JC07)
关键词
CRC
算法
VHDL
实现
Cycfic Redundancy Check, Algorithm, VHDL, Implementation
