摘要
在超长指令字结构的数字信号处理器中,其指令存储器的功耗所占比重较大。但是,根据数字信号应用的特点,可以采用循环缓冲来减小指令存储器的功耗。本文提出了一种编译器控制的循环缓冲技术,由编译器选择合适的循环代码将其放入循环缓冲,从而减小了取指过程中指令存储器的功耗;给出了循环缓冲的体系结构设计、功耗分析以及有效利用循环缓冲的编译方法;最后用功能级功耗模型验证了该方法的有效性。
For digital processing processors with the Very Long Instruction Word （VLIW） architecture, a significant amount of power is consumed in instruction memories. According to the characteristics of digital processing applications, loop buffering can be used to reduce the power consumption of instruction memories while fetching instructions. This paper presents a low power compilation method based on the compiler-controlled loop buffer where the compiler is responsible for selecting appropriate loops and putting them into the buffer. The paper gives an analysis of the power dissipation and architectural design of the loop buffer, and a compilation method to use the loop buffer effectively. Finally, the effectiveness of the proposed method is validated by a function-level power analysis model.
出处
《计算机工程与科学》
CSCD
2007年第6期93-96,112,共5页
Computer Engineering & Science
基金
国家863计划资助项目(2004AA1Z1040)
国家自然科学基金资助项目(60473079)
关键词
编译器
循环缓冲
低功耗
compiler
loop buffering
low power
