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低功耗CMOS限幅放大器设计

A low-power CMOS limiting amplifier design
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摘要 利用0.18μm CMOS工艺设计了应用于光接收机中的10Gb/s限幅放大器。此限幅放大器由输入缓冲,4级放大单元,一级用于驱动50Ω传输线的输出缓冲和失调电压补偿回路构成。输入动态范围为38dB(10mV~800mV),负载上的输出限幅在400mV,在3.3V电源电压下,功耗仅为99mW。整个芯片面积为0.8×1.3mm2。 A 10Gb/s limiting amplifier for fiber-optic transmission system is realized in a 0.18μm CMOS technology. The whole circuit consists of an input-buffer stage, four gain cells, and a output buffer for driving 50Ω transmission lines and offset compensation for offset cancellation. This limiting amplifier allows an input dynamic is rang of 38dB (10mV-800mV) and provides a constant output voltage swing (400mV), in which the power dissipation is only 99row with a supply of 3.3V and the chip area is 0.8×1.3mm^2.
出处 《电路与系统学报》 CSCD 北大核心 2007年第2期144-146,143,共4页 Journal of Circuits and Systems
关键词 CMOS模拟集成电路 限幅放大器 光接收机 CMOS analog integrated circuits, limiting amplifier, optical receiver
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参考文献7

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