摘要
提出一种基于存储器交织架构的FFT处理器设计方法,并且针对基-8FFT提出一种无冲突地址生成算法,数据按帧进行操作。每个存储器均划分为8个独立的存储体,通过对循环移位寄存器译码,蝶式运算单元并行无冲突读写操作数,8通道输入数据进行并行的复数乘法运算。每级运算引入完全流水,减少了运算的时钟周期开销,同时推导出局部流水线设计必须满足的不等式条件。输入、输出存储器采用乒乓操作,按帧轮换,FFT运算连续输入、输出,采样频率与系统工作频率一致,具有很好的实时性,运算精度通过块浮点得到保证。该设计方法可以扩展至基-16FFT处理器设计。
In this paper, memory architecture based FIT processor design methodology is presented. An efficient implementation of conflict free address generation for radix-8 algorithm is realized. Every RAM is interleaved with 8 blocks. The circulation registers are introduced and the decoding result in the conflict free addressing. Parallel processing is acquired when the butterfly elements access 8 data in a cycle. By means of pipeline in every stage, the computing is efficient in cycles. The design specification of local pipeline is also presented. With the ping-pong RAM operation in the interface module, the output data could be get continuously. By introducing the block floating point module, high accuracy is acquired without much hardware penalty. This methodology is also applicable for radix-16 FFT memory conffict free access.
出处
《微电子学与计算机》
CSCD
北大核心
2007年第3期15-19,共5页
Microelectronics & Computer
