摘要
为了对Verilog硬件描述语言(Hardware Description Language,HDL)的浮点乘法器知识产权(Intellectual Property,IP)核参数化设计方法进行详细描述,以一种浮点乘法器的参数化设计为例,介绍了其可重配置的三种功能参数,提出了尾数乘法运算采用基4Booth编码器对部分积压缩,然后采用一种将阵列与树混合的结构,对部分积划分成几个子块并行运算,最后结果用超前进位加法器累加输出。该参数化设计实例包括了由IP核的输入参数配置生成的一个单精度浮点乘法运算模块,具有四级流水线,带时钟使能端,并与IEEE754兼容。经现场可编程门阵列(Field Programmable Gate Array,FPGA)验证,结果表明参数化的设计方法使得IP核具有可重配置、可复用的优点。
Parameterized IP of floating point multiplier design method based on Verilog HDL is discussed in this paper, and three kinds of parameters are picked out. A new design method of muhiplieation operation between two fractions is pointed out, radix 4 Booth algorithm is used to compress partial products and a hybrid structure is used to divide partial products into several parts for parallel computing. The results are outputted by a carrying leading adder. As a parameterized design example, a single precision floating point multiplier module is given, which is provided with four grades of pipeline and a clock enabling port, and is compatible with IEEE754 as well. The experimental result indicates that the Parameterized Floating Point Multiplier IP core is reeonfigurable and reusable.
出处
《信息与电子工程》
2006年第5期337-341,共5页
information and electronic engineering
基金
上海市科委科研计划项目(037062026)
南通大学科研基金项目(05Z122)
关键词
参数化设计
浮点乘法器
可重配置
IP核
parameterized design
floating point multiplier
reeonfigurable
IP core
