摘要
对1.4nm超薄栅LDDnMOSFET器件栅致漏极泄漏GIDL(gate-induced drainleakage)应力下的阈值电压退化进行了研究.GIDL应力中热空穴注进LDD区界面处并产生界面态,这导致器件的阈值电压变大.相同栅漏电压VDG下的不同GIDL应力后阈值电压退化量的对数与应力VD/VDG的比值成正比.漏偏压VD不变的不同GIDL应力后阈值电压退化随着应力中栅电压的增大而增大,相同栅偏压VG下的不同GIDL应力后阈值电压退化也随着应力中漏电压的增大而增大,这两种应力情形下退化量在半对数坐标下与应力中变化的电压的倒数成线性关系,它们退化斜率的绝对值分别为0.76和13.5.实验发现器件退化随着应力过程中的漏电压变化远大于随着应力过程中栅电压的变化.
The threshold voltage （VTH） degradation have been investigated under GIDL （gate induced drain leakage） stresse in LDD nMOSFET with 1 .4nm-thick gate oxide. The trapped holes and interface states generated in the stress process at interface around LDD overlapping region result in the increase in VTH The logarithm of VTH degradation after GIDL stresses at constant VDC is proportional to the ratio of VD/VDC. The VTH degradation after GIDL stresses at constant VD increases with increasing VC in the stress, and that after GIDL stresses at constant VG increases with increasing VD in the stress In the last two cases the VTH degradation is always linear with the reciprocal of the bias which changes in the stress, and the absolute values of degradation slopes are 0.76 and 13.5, respectively. Experimental result shows that the degradation depends more strongly on VD than on VG.
出处
《物理学报》
SCIE
EI
CAS
CSCD
北大核心
2007年第3期1662-1667,共6页
Acta Physica Sinica
基金
国家自然科学基金(批准号:60376024)资助的课题.
关键词
栅致漏极泄漏
CMOS
阈值电压
栅漏电压
gate-induced drain leakage, CMOS, threshold voltage, drain-to-gate voltage
