摘要
在进行数字专用集成电路的设计中,尤其是应用于通信和信号处理领域的ASICs中,经常会遇到对一种特殊运算——平方运算的硬件实现问题。本文从常規乘法器的设计入手,通过对乘法器部分积的规律进行归纳总结和简化操作,提出了适于VLSI实现的平方器的设计方法,该方法可极大地降低硬件规模。
The problem of the hardware realization of a special operation - the square operation is often encountered in the design of digital ASICs, especially the ASICs used in communication and signal processing area. From the study of the regular multiplier designed in VLSI circuit, a realization method for the square operation suitable for VLSI implementation is proposed in this paper. By means of simplifying the part products of the multiplication, big cuts have been made in the circuit scale of the new design.
基金
国家自然科学基金
国防科委八五攻关资助项目
