期刊文献+

面向工程的SoC技术及其挑战 被引量:3

Techniques and Challenges of Engineering SoC
下载PDF
导出
摘要 系统集成芯片(SoC)是21世纪集成电路的发展方向,它以IP核复用技术、超深亚微米工艺技术和软硬件协同设计技术为支撑,是系统集成和微电子设计领域的一场革命。该文阐述了SoC的设计与验证、IP的开发与复用以及工程化SoC所面临的超深亚微米下的物理综合、软硬件协同设计、低功耗设计、可测性设计和可重用技术等方面的挑战。 As a development direction of IC in 21^st century, SoC, based on IP core reusing technique, very deep sub-micron technique, co-design of software and hardware technique, is a revolution in system integration and mieroelectronic design. The challenges in design and verification of SoC, development and reuse of IP core and physical synthesis in very deep sub-micron, co-design of software and hardware, low pawer design, design for test and reusability technique of engineering oriented SoC are described.
出处 《计算机工程》 EI CAS CSCD 北大核心 2006年第23期229-231,共3页 Computer Engineering
关键词 集成电路 系统集成芯片 知识产权核 超深亚微米 协同设计 Integration circuit System on Chip(Sot) IP core Very deep sub-micron Co-design
  • 相关文献

参考文献8

二级参考文献117

共引文献86

同被引文献13

  • 1徐志军,邱传飞,曲宁.集成电路设计的现状与发展[J].军事通信技术,2006,27(4):26-30. 被引量:1
  • 2MARK ALLEN WEISS.Data Structures and Algorithm Analysis inC++[M].2rd ed.北京:清华大学出版,2002. 被引量:1
  • 3ZHANG Jinyi, CHEN Wenwei, RUN Xiaojun, et al. A System-levelmixed DFT-TAM Structure for SOC Design[C]//High Density Micro-system Design and Packaging and Component Failure Analysis Conf. Shanghai, China: [s.n.], 2005: 01-04. 被引量:1
  • 4LIU Xinfu, WU K Y, JU Jianghua, et al. Deep Sub-micron Ultra-low Power CMOS Device Design and Optimization[C]//Int Workshop on Junction Technology.Shanghai, China: [s.n.], 2004: 328-330. 被引量:1
  • 5WONG A C W, KATHIRESAN G. A 1V Wireless Transceiver for an Ultra Low Power SOC for Biotelemetry Applications[C]// European Solid State Circuits Conf.. Abingdon: Toumaz Technol. Ltd., 2007: 127-130. 被引量:1
  • 6XU Yongjun, LUO Zuying. Average Leakage Current Macro Modeling for Duahhreshold Voltage Circuits[C]//Proceedings of the 12^th IEEE Asian Test Symposium. Xi' an: [s.n.], 2003: 196-201. 被引量:1
  • 7TAWFIK S A, KURSUN V. Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs[J]. IEEE Transactions on Electron Devices, 2008(55): 302-306. 被引量:1
  • 8TAWFIK S A, KURSUN V. Low Power and High Speed Multi Threshold Voltage Interface Circuits[J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2009(17): 638-645. 被引量:1
  • 9Keating M, Flynn D, Aitken R, et al. Low Power Methodology Manual for System - on - Chip De- sign[ M ]. Springer,2007:222 - 233. 被引量:1
  • 10孟李林.从SOC到NOC的集成电路设计技术发展[J].半导体技术,2008,33(3):190-192. 被引量:10

引证文献3

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部