摘要
提出了一种基于现场可编程门阵列(FPGA)的数字交叉IP核的设计方法。整个设计使用自顶而下的方式,采用Verilog HDL进行描述,并给出了硬件的实现。仿真结果表明,该交叉IP核可以实现256×256无阻塞交叉矩阵。此法简单、高效,非常适合中小规模的交叉矩阵实现。
This paper proposes one solution of design for digital switch IP core based on field programmable gate array （FPGA）. The method of top-down is applied in the solution, and it is fulfilled in hardware with Verilog HDL. The simulation results show that the IP core can realize the non-blocking switching matrix of 256 × 256. The solution is simple and more efficient, so it is very suitable for implementing medium and small scale switching matrix.
出处
《重庆邮电学院学报（自然科学版）》
2006年第2期197-200,共4页
Journal of Chongqing University of Posts and Telecommunications(Natural Sciences Edition)
基金
国家"863"重大项目(2005AA123780)
重庆市科委资助项目(CSTC
2005AAC2040)
重庆市经委资助项目(05-1GX-DZ180)
