摘要
本文着重研究全数字接收机中定时恢复环路的设计,该环路由内插滤波器,预滤波器,平方定时误差检测,环路滤波和 定时控制单元组成,仿真结果表明,通过预滤波明显减小了定时抖动,该算法可以达到较好的性能,并由单片FPGA实现, 该芯片已成功用于QAM全数字接收机中。
This paper discuss the design of timing recovery, loop in ALL Digital Receivers.The loop is composed ofinterpolating filter, prefilter, squring timing-error detector.loop filter and timing contral unit.The sirnulation results sbow that the squaring timing recovery with prefiter can obviously reduce the timing jitter, The method shows a superior performartce and realized in a single chip FPGA.which has been successfully used in All-digitized QAM Receiver.
关键词
全数字接收机
平方定时恢复
预滤波
内插滤波器
ALL Digital Reeeivers
squaring timing recovery
prcfilter
interpolating filter
