摘要
由于网络带宽的提高和IPSec协议的引入,有必要用硬件方式实现分组加密等计算密集型的任务以改善关键网络设备的安全处理性能和实时性.采用可重配置硬件,设计了一个用于IPSec协议的AES核;在对AES算法分析的基础上,对关键单元的硬件设计进行了优化.仿真和实验测试结果表明,本文设计的AES核在CBC工作模式下可以稳定地工作于52.6MH z,数据吞吐量达610M bps.
With the increase of network bandwidth and the application of Internet Protocol Security （IPSec）, it is necessary to implement the compute-intensive portions of IPSec, such as block cipher algorithm, by hardware to improve the security performance and real-time requirement of the key equipments. In this paper, a reconfigurable hardware implementation of Advanced Encryption Standard （AES） core for IPSec is proposed. The design of the key unit is optimized based on the analysis of AES. Simulation and experiment results show that in the Cipher-Block Chaining （CBC） mode, the core can work steadily at 52. 6MHz and the throughout rate is about 610Mbps.
出处
《小型微型计算机系统》
CSCD
北大核心
2005年第12期2082-2086,共5页
Journal of Chinese Computer Systems
基金
国防基础研究项目(J1300B005)资助
关键词
网际安全协议
高级加密标准
硬件实现
现场可编程门阵列
Internet protocol security
advanced encrypt standard
hardware implementation
field programmable gate array
