摘要
提出了一种用于片上全局互连的混合插入方法.该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点,将它们混合插入到连线的合适位置,从而降低互连的延时和功耗.模拟结果表明,该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.
A hybrid insertion scheme for on-chip global interconnects is presented. The scheme takes advantages of repeaters and low-swing differential-signaling circuits on driving long wires in different length, and optimally inserts them along the wire in order to decrease delay and power of interconnects. It is shown that the delay, energy, delay-energy-product, and area are all considerably decreased compared with other available schemes.
基金
国家高技术研究发展计划(批准号:2004AA1Z1040)
国家自然科学基金(批准号:60473079)资助项目~~
关键词
片上互连
延时
能耗
面积
低摆幅
差分信号
on-chip interconnect
delay
energy
area
low-swing
differential-signaling
