摘要
提出了低功耗架构、片上总线预选器等新的设计思想和改进的高阶布斯算法,利用0.35μmCMOS工艺,研制成功一种低功耗、高性能32位浮点精简指令系统(RISC)微处理器.该处理器芯片内置128kb静态随机存储器,芯片面积为7mm×7mm,中断和定、浮点等指令集所有指令运行正确,32位浮点乘法运算仅需17.8ns.与传统的设计相比,该微处理器主频提高了38%,功耗下降了39%,50MHz频率下的动态功耗仅为164mW,并具有边界扫描测试功能.研制结果表明,新的设计思想和算法有效地提高了微处理器的综合性能,为嵌入式浮点RISC的研究提供了新的途径.
A 32-bit floating-point reduced instruction set computer (RISC) microprocessor with high-performance and low-power consumption has been successfully fabricated in 0.35 μm CMOS technology. Three million transistors are integrated on a 7 mm × 7 mm die housed in a 180-pin grid array (PGA). The processor has 4-stage pipeline, 32-bit floating-point arithmetic and logic unit (ALU), 32-bit floating-point multiplier, and 128 kb static random access memory (SRAM). Several innovative aspects are introduced in the control and datapath architecture levels including low-power datapath architecture for saving power, modified high radix Booth algorithm for fast 32-bit fixed-point and floating-point multiplication or division, and embedded bus preselector improving the performance of bus interface. The simulation results indicate that the power consumption of the processor can be reduced by 39%, and the operation frequency is increased by 38%. The chip testing shows that each instruction and its random combinations run correctly, and the power consumption of the chip is less than 164 mW at 50 MHz clock rate and 3.3 V power supply.
出处
《西安交通大学学报》
EI
CAS
CSCD
北大核心
2005年第6期607-610,655,共5页
Journal of Xi'an Jiaotong University
