摘要
基于SOC(systemonchip)技术,利用VHDL语言设计开发具有奇偶校验功能、数据位和波特率可调的通用异步串行通信接口IP核。该IP核内置异步接收和发送模块,可直接提供给其它SOC系统设计者使用,减少SOC系统设计的工作量。
By means of SOC technology, the UART IP core is designed by VHDL language. The UART core comprises transmit and receive unit, supporting even or odd parity, controllable baud rate and serial data format. If necessary, the IP core can be adopted by other engineers immediately with no difficulty, reducing the work of SOC designing.
出处
《微计算机信息》
北大核心
2005年第4期132-133,100,共3页
Control & Automation
