摘要
随着集成电路生产工艺的进展,互连线在集成电路设计中的影响越来越大。为了减小互连线的影响,通常在芯片互连中插入缓冲器,但这样做会增加时延。因此,为了精确地对系统进行时延估计,必须对缓冲器的时延进行估算。基于Sakurai的器件模型,提出了一种新的缓冲器时延估算模型。
With the development of IC process technology, the impact of interconnects on the design of IC's is becoming greater. In order to decrease the effect, buffers are generally inserted into interconnects of IC's, which, however, introduces other delays. Therefore, it is necessary to estimate the delay of buffers for system design. Based on Sakurai's MOS model, a new delay model for CMOS buffers is proposed in the paper.
出处
《微电子学》
CAS
CSCD
北大核心
2004年第5期540-542,共3页
Microelectronics
基金
国家863计划资助项目(2002AA1Z1520)
上海市AM基金(0110)资助项目。
