摘要
从门电路标准延迟模型出发 ,在超前进位加法器单元电路优化的基础上 ,给出了超前进位加法器延迟时间公式 ,阐明了公式中各项的意义 .推导出模块延迟时间公式、最大级联数 Km( max) 、最优分组方案等重要结果 .并与功耗、面积约束一起 ,归纳出超前进位加法器的优化设计规则 .
The delay time formulae of the carry lookahead adders(CLA) were given based on the standard delayed model of logic gate and optimal circuit unit. The meaning of all terms in the formulae was expounded. The formulae were verified by a three slloreys sixty-four bit CLA. The delay time formulae of the module of CLA,the maximum cascade number and the optimal layout of grouping,the above valuable results were deducted. The optimal design rule of CLA was inducted from power dissipation and area constraint,reflected by maximum fanout and speed constraint. With its regular structure,32-bit CLA designed according above rule had a fanout no more than 7 and a critical path logic depth of 6.
出处
《武汉理工大学学报（交通科学与工程版）》
北大核心
2004年第4期585-588,共4页
Journal of Wuhan University of Technology（Transportation Science & Engineering）
基金
国家民委科研基金项目资助 (批准号 :990 10 1)
