摘要
提出基于比特平面的快速中值滤波算法硬件实现结构和核心处理电路,在减少了中值滤波电路面积的情况下,显著提高了处理速度。提出的比特平面算法硬件实现结构的面积与滤波数据长度和量化比特数成近似线性关系,适于各种滤波窗口大小和数据精度的中值滤波;算法硬件实现结构规则,特别适于用FPGA实现。
A new median filter hardware architecture and processing element circuit based on bit planes algorithm is introduced in this paper.The processing time and circuit area are efficiently saved in the new median filter,and the circuit area of the hardware architecture presented in this paper is linear with the median filter data and quantitative bit numbers.The proposed hardware structure is regular and suitable for FPGA implementation.
出处
《电视技术》
北大核心
2009年第S1期73-74,80,共3页
Video Engineering
