摘要
超大规模集成电路设计进入深亚微米阶段 ,衬底和互连线的寄生RC参数成为影响电路速度和信号完整性分析的关键因素 由于互连提取的RC规模十分庞大 ,对其进行时序分析十分困难 ,因此需要对提取的RC网络进行约简 在经典的RC网络约简算法PACT的基础上提出几点重要改进 ,明显地提高了网络约简的速度 ,改进后的算法克服了经典PACT算法的局限性 ,使之可以适用于含有到端口无直流通路的内点的电路 ,从而提高了该算法的适用性 计算结果表明 ,在精度保持不变的条件下 。
With the development of deep sub-micron VLSI design, the behavior of parasitic RCs derived from substrate and inter-connection becomes key factor of affecting circuit speed and signal integrity. Generally, the extracted RCs constitute a very large scale network that needs reduction to fit for efficient timing analysis. Several important modifications have been made to the classic RC network reduction algorithm PACT that significantly improved the performance of network reduction. At the same time, the algorithm overcame the limitation of the classic PACT algorithm, being capable of handling the internal nodes without any DC path to ports of the RC netlist. Computation results show that the modified algorithm is several times faster than the classic PACT algorithm without losing any computational accuracy.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2004年第4期407-413,共7页
Journal of Computer-Aided Design & Computer Graphics
