摘要
本文提出一种用RC网络作延迟模型进行开关级定时模拟的方案.此方案把开关级定时模拟划分为求解将来状态和计算状态变化的延迟两个步骤来进行.文中讨论了延迟模型的建立及延迟计算中的有关问题.按照所述方案,开发了一个适用于MOS VLSI逻辑模拟及延迟估算的计算机程序LOMOS.实践表明,LOMOS模拟出的信号延迟时间同电路模拟程序SPICEII相比误差通常在30％以内,模拟速度要快近三个数量级.
A new method for switch-level timing simulation is proposed.We suggest that the timingsimulation should be performed by two steps.First,the future state is evaluated.Then,someRC networks are constructed to calculate signal delay.The issues on implementation of signaldelay calculation and construction of RC network delay model are discussed. A computer pro-gram LOMOS (LOgic simulator for MOS digital circuits) is developed.Experiments show thatLOMOS runs two to three orders of magnitude faster than SPICE with delay errors fallingwithin 30% usually.
关键词
逻辑模拟
开关级模型
RC网络
IC
Logic simulation
Switch-level model
Switchlevel simulation
VLSI
MOS digital integrated circuits
