摘要
谐波检测中数字低通滤波器的设计是关键。本文通过选用现场可编程逻辑器件(FPGA)确定了数字低通滤波器的硬件实现方案,并按照层次化、模块化、参数化的设计思路,采用VHDL硬件描述语言进行了硬件设计并进行了仿真验证,为电力有源滤波器谐波检测中低通滤波器设计提供了参考。
The key of harmonic detection is the design of digital lowpass filter. In this paper, a scheme of hardware implementation of digital lowpass filter is worked out by selecting FPGA, From the clew of implementing a stratified , modularized and parameterized design, the thesis describes the hardware implementation of digital lowpass filter with VHDL, the design is simulated and show that it is correct and provide reference to the design of digital lowpass filter of APF harmonic diction.
出处
《中国集成电路》
2007年第9期53-57,共5页
China lntegrated Circuit
