摘要
在集成电路可制造性设计研究中,成品率与可靠性之间的关系模型备受人们关注.缺陷对成品率和可靠性的影响不仅与出现在芯片上的缺陷粒径大小有关而且与缺陷出现在芯片上的位置有关.本文主要考虑了出现在互连线上的金属丢失物缺陷对互连线的影响,分析了同一粒径的缺陷出现在互连线不同位置对互连线有效宽度的影响,给出了基于缺陷均匀分布的互连线平均有效宽度,结合已有成品率和可靠性估计模型,提出了基于缺陷位置信息的集成电路制造成品率与可靠性之间的关系模型.在工艺线稳定的情况下,利用该工艺线的制造成品率可以通过该关系式有效地估计出产品的可靠性,从而有效地缩短新产品的研发周期.
In the study of IC design for manufacturing, models on the relationship of yield and reliability deserve much attention. The impact of defects on the yield and reliability is associated not only with the particle size of it but also with the location of it on the chip. In this paper, it is analyzed that the defects at the same size in interconnect different locations affect the effective width of interconnect wires, by discussing the impact of the loss of metal in the interconnect wire on the interconnect wire itself. The average effective width of interconnect wires is given based on the uniform distribution of defects.in addition,the model on the relationship of the IC manufacturing yield and reliability is presented based on the location of defects, by referring on the existing model of estimating yield and reliability.If the processing line is stable,the rate of the product failure can be estimated effectively by the expression and the yield of the processing line, which can shorten the development period of the new products.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2012年第8期1665-1669,共5页
Acta Electronica Sinica
基金
陕西省科技厅计划项目(No.SJ08-ZT13)
关键词
成品率
可靠性
缺陷
粒径分布
yield
reliability
defect
the size distribution of defect
