In the past decade, micro-electromechanical systems （MEMS）-based thermoelectric infrared （IR） sensors have received considerable attention because of the advances in micromachining technology. This paper presents ...In the past decade, micro-electromechanical systems （MEMS）-based thermoelectric infrared （IR） sensors have received considerable attention because of the advances in micromachining technology. This paper presents a review of MEMS-based thermoelectric IR sensors. The first part describes the physics of the device and discusses the figures of merit. The second part discusses the sensing materials, thermal isolation micro- structures, absorber designs, and packaging methods for these sensors and provides examples. Moreover, the status of sensor implementation technology is examined from a historical perspective by presenting findings from the early years to the most recent findings.展开更多
To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were iden...To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.展开更多
Electro-deposition, electrical activation, thermal oxidation, and reactive ion sputtering are the four primary methods to fabricate iridium oxide film. Among these methods, reactive ion sputtering is a commonly used m...Electro-deposition, electrical activation, thermal oxidation, and reactive ion sputtering are the four primary methods to fabricate iridium oxide film. Among these methods, reactive ion sputtering is a commonly used method in standard micro-fabrication processes. In different sputtering conditions, the component, texture, and electrochemistry character of iridium oxide varies considerably. To fabricate the iridium oxide film compatible with the wafer-level processing of neural electrodes, the quality of iridium oxide film must be able to withstand the mechanical and chemical impact of post-processing, and simultaneously achieve good performance as a neural electrode. In this study, parameters of sputtering were researched and developed to achieve a balance between mechanical stability and good electrochemical characteristics of iridium oxide film on electrode. Iridium oxide fabricating process combined with fabrication flow of silicon electrodes, at wafer-level, is introduced to produce silicon based planar iridium oxide neural electrodes. Compared with bare gold electrodes, iridium oxide electrodes fabricated with this method exhibit particularly good electrochemical stability, low impedance of 386 kW at 1 kH z, high safe charge storage capacity of 3.2 m C/cm^2, and good impedance consistency of less than 25% fluctuation.展开更多
A new wafer-level 3D packaging structure with Benzocyclobutene（BCB）as interlayer dielectrics（ILDs） for multichip module fabrication is proposed for application in the Ku-band wave.The packaging structure consists ...A new wafer-level 3D packaging structure with Benzocyclobutene（BCB）as interlayer dielectrics（ILDs） for multichip module fabrication is proposed for application in the Ku-band wave.The packaging structure consists of two layers of BCB films and three layers of metallized films,in which the monolithic microwave IC（MMIC）,thin film resistors,striplines and microstrip lines are integrated.Wet etched cavities fabricated on the silicon substrate are used for mounting active and passive components.BCB layers cover the components and serve as ILDs for interconnections.Gold bumps are used as electric interconnections between different layers,which eliminates the need to prepare vias by costly dry etching and deposition processes.In order to get high-quality BCB films for the subsequent chemical mechanical planarization（CMP）and multilayer metallization processes,the BCB curing profile is optimized and the roughness of the BCB film after the CMP process is kept lower than 10 nm.The thermal,mechanical and electrical properties of the packaging structure are investigated.The thermal resistance can be controlled below 2℃/W.The average shear strength of the gold bumps on the BCB surface is around 70 N/mm^2.The performances of MMIC and interconnection structure at high frequencies are optimized and tested.The S-parameters curves of the packaged MMIC shift slightly showing perfect transmission character.The insertion loss change after the packaging process is less than 1 dB range at the operating frequency and the return loss is less than –8 dB from 10 to 15 GHz.展开更多
文摘In the past decade, micro-electromechanical systems （MEMS）-based thermoelectric infrared （IR） sensors have received considerable attention because of the advances in micromachining technology. This paper presents a review of MEMS-based thermoelectric IR sensors. The first part describes the physics of the device and discusses the figures of merit. The second part discusses the sensing materials, thermal isolation micro- structures, absorber designs, and packaging methods for these sensors and provides examples. Moreover, the status of sensor implementation technology is examined from a historical perspective by presenting findings from the early years to the most recent findings.
基金Projects(51475072,51171036)supported by the National Natural Science Foundation of China
文摘To reveal the drop failure modes of the wafer level chip scale packages （WLCSPs） with Sn-3.0Ag-0.5Cu solder joints, board level drop tests were performed according to the JEDEC standard. Six failure modes were identified, i.e., short FR-4 cracks and complete FR-4 cracks at the printing circuit board （PCB） side, split between redistribution layer （RDL） and Cu under bump metallization （UBM）, RDL fracture, bulk cracks and partial bulk and intermetallic compound （IMC） cracks at the chip side. For the outmost solder joints, complete FR-4 cracks tended to occur, due to large deformation of PCB and low strength of FR-4 dielectric layer. The formation of complete FR-4 cracks largely absorbed the impact energy, resulting in the absence of other failure modes. For the inner solder joints, the absorption of impact energy by the short FR-4 cracks was limited, resulting in other failure modes at the chip side.
基金supported by the National Natural Science Foundation of China(Grant Nos.61335010,61275145,61275200&61275145)the National Hi-Tech Research and Development Program of China("863"Project)(Grant No.2013AA032204)+1 种基金the Brain Vanguard Technology Crossover Cooperation Projects of Chinese Academy of Sciences(GrantNo.KJZD-EW-L11-01)the Recruitment Program for Young Professionals
文摘Electro-deposition, electrical activation, thermal oxidation, and reactive ion sputtering are the four primary methods to fabricate iridium oxide film. Among these methods, reactive ion sputtering is a commonly used method in standard micro-fabrication processes. In different sputtering conditions, the component, texture, and electrochemistry character of iridium oxide varies considerably. To fabricate the iridium oxide film compatible with the wafer-level processing of neural electrodes, the quality of iridium oxide film must be able to withstand the mechanical and chemical impact of post-processing, and simultaneously achieve good performance as a neural electrode. In this study, parameters of sputtering were researched and developed to achieve a balance between mechanical stability and good electrochemical characteristics of iridium oxide film on electrode. Iridium oxide fabricating process combined with fabrication flow of silicon electrodes, at wafer-level, is introduced to produce silicon based planar iridium oxide neural electrodes. Compared with bare gold electrodes, iridium oxide electrodes fabricated with this method exhibit particularly good electrochemical stability, low impedance of 386 kW at 1 kH z, high safe charge storage capacity of 3.2 m C/cm^2, and good impedance consistency of less than 25% fluctuation.
文摘A new wafer-level 3D packaging structure with Benzocyclobutene（BCB）as interlayer dielectrics（ILDs） for multichip module fabrication is proposed for application in the Ku-band wave.The packaging structure consists of two layers of BCB films and three layers of metallized films,in which the monolithic microwave IC（MMIC）,thin film resistors,striplines and microstrip lines are integrated.Wet etched cavities fabricated on the silicon substrate are used for mounting active and passive components.BCB layers cover the components and serve as ILDs for interconnections.Gold bumps are used as electric interconnections between different layers,which eliminates the need to prepare vias by costly dry etching and deposition processes.In order to get high-quality BCB films for the subsequent chemical mechanical planarization（CMP）and multilayer metallization processes,the BCB curing profile is optimized and the roughness of the BCB film after the CMP process is kept lower than 10 nm.The thermal,mechanical and electrical properties of the packaging structure are investigated.The thermal resistance can be controlled below 2℃/W.The average shear strength of the gold bumps on the BCB surface is around 70 N/mm^2.The performances of MMIC and interconnection structure at high frequencies are optimized and tested.The S-parameters curves of the packaged MMIC shift slightly showing perfect transmission character.The insertion loss change after the packaging process is less than 1 dB range at the operating frequency and the return loss is less than –8 dB from 10 to 15 GHz.
