模块化多电平换流器型直流输电系统(modular multilevel converter based high voltage direct current,MMCHVDC)和交流线路可为重要负荷双路供电,因此MMCHVDC需具备在联网运行状态和孤岛运行状态间稳定转换的能力。该文分析了MMC在联...模块化多电平换流器型直流输电系统(modular multilevel converter based high voltage direct current,MMCHVDC)和交流线路可为重要负荷双路供电,因此MMCHVDC需具备在联网运行状态和孤岛运行状态间稳定转换的能力。该文分析了MMC在联网状态和孤岛状态间相互转换的过程,并设计了一种基于本地电气量的MMC控制模式切换策略。之后,对MMC无源供电控制器进行改进,设计了一种无需切换控制模式的MMC下垂控制策略。最后,通过PSCAD仿真对上述2种转换策略进行验证和比较,结果表明2种策略均能使MMC在联网状态和孤岛状态间稳定转换。2种策略各有优缺点,实际应用中MMC需依据具体的控制目标选取合适的策略。展开更多
A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18μm CMOS technology is proposed. It is based on a current steering segmented 6＋6 architecture and requires no calibration. ...A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18μm CMOS technology is proposed. It is based on a current steering segmented 6＋6 architecture and requires no calibration. By dividing one most significant bit unary source into 16 elements located in 16 separated regions of the array, the linear gradient errors and quadratic errors can be averaged and eliminated effectively. A novel static performance testing method is proposed. The measured differential nonlinearity and integral nonlinearity are 0.42 and 0.39 least significant bit, respectively. For 12-bit resolution, the converter reaches an update rate of 100 MS/s. The chip operates from a single 1.8 V voltage supply, and the core die area is 0.28 mm^2.展开更多
An active crowbar protective circuit is an effective and common approach for low voltage ride through(LVRT) of a doubly-fed induction generator(DFIG). The crowbar resistance value and its switching scheme both have cr...An active crowbar protective circuit is an effective and common approach for low voltage ride through(LVRT) of a doubly-fed induction generator(DFIG). The crowbar resistance value and its switching scheme both have crucial effects on safety recovery. The effects encountered are correlative dependence and interplay so that analyzing them from a single factor, as most existing LVRT control methods would do, obtains a partial optimal solution. This paper combines these two factors toanalyze their coordination effects on the LVRT control,and to also investigate whether the global optimal performance of these factors can be achieved. The principles for resistance selection and the schemes for crowbar switching are discussed first. Next, the coupling relationship is ana-lyzed based on statistical sampling simulation data with different resistance values and various switching schemes.The results demonstrate that their coordination has critical influence on rotor peak current, DC-link voltage and reactive power. The optimal coordination will be different according to specific requirements. Hence the global optimal combination could be achieved when all requirements are taken into consideration.展开更多
This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split...This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter （DAC）. In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio （SNDR） of 57.5 dB and spurious-free dynamic range （SFDR） of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2.展开更多
文摘模块化多电平换流器型直流输电系统(modular multilevel converter based high voltage direct current,MMCHVDC)和交流线路可为重要负荷双路供电,因此MMCHVDC需具备在联网运行状态和孤岛运行状态间稳定转换的能力。该文分析了MMC在联网状态和孤岛状态间相互转换的过程,并设计了一种基于本地电气量的MMC控制模式切换策略。之后,对MMC无源供电控制器进行改进,设计了一种无需切换控制模式的MMC下垂控制策略。最后,通过PSCAD仿真对上述2种转换策略进行验证和比较,结果表明2种策略均能使MMC在联网状态和孤岛状态间稳定转换。2种策略各有优缺点,实际应用中MMC需依据具体的控制目标选取合适的策略。
基金Project supported by the National High Technology Research and Development Program of China(No.2008AA010700)
文摘A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18μm CMOS technology is proposed. It is based on a current steering segmented 6＋6 architecture and requires no calibration. By dividing one most significant bit unary source into 16 elements located in 16 separated regions of the array, the linear gradient errors and quadratic errors can be averaged and eliminated effectively. A novel static performance testing method is proposed. The measured differential nonlinearity and integral nonlinearity are 0.42 and 0.39 least significant bit, respectively. For 12-bit resolution, the converter reaches an update rate of 100 MS/s. The chip operates from a single 1.8 V voltage supply, and the core die area is 0.28 mm^2.
基金supported by the National Natural Science Foundation of China (No. 61773137, No. 61403099)the National Natural Science Foundation of Shandong Province (No. 2014BSA10007, No. 2014J14LN92)
文摘An active crowbar protective circuit is an effective and common approach for low voltage ride through(LVRT) of a doubly-fed induction generator(DFIG). The crowbar resistance value and its switching scheme both have crucial effects on safety recovery. The effects encountered are correlative dependence and interplay so that analyzing them from a single factor, as most existing LVRT control methods would do, obtains a partial optimal solution. This paper combines these two factors toanalyze their coordination effects on the LVRT control,and to also investigate whether the global optimal performance of these factors can be achieved. The principles for resistance selection and the schemes for crowbar switching are discussed first. Next, the coupling relationship is ana-lyzed based on statistical sampling simulation data with different resistance values and various switching schemes.The results demonstrate that their coordination has critical influence on rotor peak current, DC-link voltage and reactive power. The optimal coordination will be different according to specific requirements. Hence the global optimal combination could be achieved when all requirements are taken into consideration.
基金supported by the National Natural Science Foundation of China(No.61401097)
文摘This paper presents a 10 bit successive approximation register （SAR） analog-to-digital converter （ADC） in 0.18 μm 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter （DAC）. In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio （SNDR） of 57.5 dB and spurious-free dynamic range （SFDR） of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm2.
