We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improve...We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improved to below 10 ps RMS. We then further evaluate waveform-timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.展开更多
A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplificat...A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplification phase.This circuit permits the common-mode voltage of the sample signal to reach full swing.Using the charge-complement technique,the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively.Simulation results show that as sample signal common-mode voltage changes,the difference between the minimum and maximum gain error is less than 0.03%.When the capacitor mismatch is increased from 0 to 0.2%,the gain error is deteriorated by 0.00015%）.In all simulations,the gain of amplifier is 69 dB.展开更多
This paper presents a third-order single-loop delta-sigma modulator of a biomedical micro-system for portable electroencephalogram（EEG） monitoring applications.To reduce the power consumption,the loop filter of the ...This paper presents a third-order single-loop delta-sigma modulator of a biomedical micro-system for portable electroencephalogram（EEG） monitoring applications.To reduce the power consumption,the loop filter of the proposed modulator is implemented by applying a switched-capacitor structure.The modulator is designed in a 0.35-μm 2P4M standard CMOS process,with an active area of 365×290μm^2.Experimental results show that this modulator achieves a 68 dB dynamic range with an input sinusoidal signal of 100 Hz signal bandwidth under a 64 over-sampling ratio.The whole circuit consumes 515μW under a 2.5 V power supply,which is suitable for portable EEG monitoring.展开更多
结合 T 型开关电容积分器和 Nagaraj 开关电容积分器,设计出了新的超大时间数(VLTC)开关电容积分器的电路结构,可以将等效电容比率分解成三项比例乘积的形式,从而提高开关电容电路的面积效率.结构对运放性要求不高,易于超大时间常数积...结合 T 型开关电容积分器和 Nagaraj 开关电容积分器,设计出了新的超大时间数(VLTC)开关电容积分器的电路结构,可以将等效电容比率分解成三项比例乘积的形式,从而提高开关电容电路的面积效率.结构对运放性要求不高,易于超大时间常数积分器的全集成.展开更多
为降低流水线模数转换器(ADC)中跨导运算放大器(OTA)设计要求,在分析已有开关电容电路(SC)误差消除技术和流水线ADC误差源的基础上,提出一种改进的流水线ADC开关电容电路及与其匹配的OTA设计方案。采用交叉差分结构,对虚地电容进行了修...为降低流水线模数转换器(ADC)中跨导运算放大器(OTA)设计要求,在分析已有开关电容电路(SC)误差消除技术和流水线ADC误差源的基础上,提出一种改进的流水线ADC开关电容电路及与其匹配的OTA设计方案。采用交叉差分结构,对虚地电容进行了修正,并将电容失配参数在系统传输函数中消去,使开关电容电路对OTA的增益误差要求降低,并使其瞬态功耗下降。采用CM O S 0.18μm工艺设计了一个分辨率为8位、取样速率200 MH z的ADC作为验证原型,仿真结果表明,该优化结构符合ADC电路高速低功耗要求,可作为信号前端处理模块应用到模数转换电路中。展开更多
基金Supported by Knowledge Innovation Program of the Chinese Academy of Sciences(KJCX2-YW-N27)National Natural Science Foundation of China(11175176)
文摘We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improved to below 10 ps RMS. We then further evaluate waveform-timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.
基金supported by the National Natural Science Foundation of China(Nos.61036004,61076024)
文摘A switched-capacitor amplifier with an accurate gain of two that is insensitive to component mismatch is proposed.This structure is based on associating two sets of two capacitors in cross series during the amplification phase.This circuit permits the common-mode voltage of the sample signal to reach full swing.Using the charge-complement technique,the proposed amplifier can reduce the impact of parasitic capacitors on the gain accuracy effectively.Simulation results show that as sample signal common-mode voltage changes,the difference between the minimum and maximum gain error is less than 0.03%.When the capacitor mismatch is increased from 0 to 0.2%,the gain error is deteriorated by 0.00015%）.In all simulations,the gain of amplifier is 69 dB.
基金Project supported by the National Natural Science Foundation of China(Nos.60776024,60877035,90820002,60976026)the National High Technology Research and Development Program of China(Nos.2007AA04Z329,2007AA04Z254).
文摘This paper presents a third-order single-loop delta-sigma modulator of a biomedical micro-system for portable electroencephalogram（EEG） monitoring applications.To reduce the power consumption,the loop filter of the proposed modulator is implemented by applying a switched-capacitor structure.The modulator is designed in a 0.35-μm 2P4M standard CMOS process,with an active area of 365×290μm^2.Experimental results show that this modulator achieves a 68 dB dynamic range with an input sinusoidal signal of 100 Hz signal bandwidth under a 64 over-sampling ratio.The whole circuit consumes 515μW under a 2.5 V power supply,which is suitable for portable EEG monitoring.
文摘为降低流水线模数转换器(ADC)中跨导运算放大器(OTA)设计要求,在分析已有开关电容电路(SC)误差消除技术和流水线ADC误差源的基础上,提出一种改进的流水线ADC开关电容电路及与其匹配的OTA设计方案。采用交叉差分结构,对虚地电容进行了修正,并将电容失配参数在系统传输函数中消去,使开关电容电路对OTA的增益误差要求降低,并使其瞬态功耗下降。采用CM O S 0.18μm工艺设计了一个分辨率为8位、取样速率200 MH z的ADC作为验证原型,仿真结果表明,该优化结构符合ADC电路高速低功耗要求,可作为信号前端处理模块应用到模数转换电路中。
