A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-fo...A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.展开更多
采用标准0.18 μm CMOS工艺,设计了一种高锁定范围的半盲型过采样时钟数据恢复电路.该时钟数据恢复电路（Clock and Data Recovery,CDR）主要由鉴频器（Frequency detector,FD）、多路平行过采样电路、10位数模转换器（Digital To Analo...采用标准0.18 μm CMOS工艺,设计了一种高锁定范围的半盲型过采样时钟数据恢复电路.该时钟数据恢复电路（Clock and Data Recovery,CDR）主要由鉴频器（Frequency detector,FD）、多路平行过采样电路、10位数模转换器（Digital To Analog Converter,DAC）、低通滤波器（Low Pass Filter,LPF）、多相位压控振荡器（Voltage Controlled Oscillator,VCO）等构成.该CDR电路采用模数混合设计方法,并提出了基于双环结构实现对采样时钟先粗调后微调的方法,并且在细调过程中提出了加权调相的方法缩短采样时间.仿真结果表明,该CDR电路能恢复1.25～4.00 Gbps之间的伪随机数据电路,锁定时间为2.1 μs,VCO输出的抖动为47.12 ps.展开更多
基金supported by National Natural Science Foundation of China under Grant 62174132the Fundamental Research Funds for Central Universities under Grant xzy022022060.
文摘A 28/56 Gb/s NRZ/PAM-4 dual-mode transceiver(TRx)designed in a 28-nm complementary metal-oxide-semiconduc-tor(CMOS)process is presented in this article.A voltage-mode(VM)driver featuring a 4-tap reconfigurable feed-forward equal-izer(FFE)is employed in the quarter-rate transmitter(TX).The half-rate receiver(RX)incorporates a continuous-time linear equal-izer(CTLE),a 3-stage high-speed slicer with multi-clock-phase sampling,and a clock and data recovery(CDR).The experimen-tal results show that the TRx operates at a maximum speed of 56 Gb/s with chip-on board(COB)assembly.The 28 Gb/s NRZ eye diagram shows a far-end vertical eye opening of 210 mV with an output amplitude of 351 mV single-ended and the 56 Gb/s PAM-4 eye diagram exhibits far-end eye opening of 33 mV(upper-eye),31 mV(mid-eye),and 28 mV(lower-eye)with an output amplitude of 353 mV single-ended.The recovered 14 GHz clock from the RX exhibits random jitter(RJ)of 469 fs and deterministic jitter(DJ)of 8.76 ps.The 875 Mb/s de-multiplexed data features 593 ps horizontal eye opening with 32.02 ps RJ,at bit-error rate(BER)of 10-5(0.53 UI).The power dissipation of TX and RX are 125 and 181.4 mW,respectively,from a 0.9-V sup-ply.
文摘采用标准0.18 μm CMOS工艺,设计了一种高锁定范围的半盲型过采样时钟数据恢复电路.该时钟数据恢复电路（Clock and Data Recovery,CDR）主要由鉴频器（Frequency detector,FD）、多路平行过采样电路、10位数模转换器（Digital To Analog Converter,DAC）、低通滤波器（Low Pass Filter,LPF）、多相位压控振荡器（Voltage Controlled Oscillator,VCO）等构成.该CDR电路采用模数混合设计方法,并提出了基于双环结构实现对采样时钟先粗调后微调的方法,并且在细调过程中提出了加权调相的方法缩短采样时间.仿真结果表明,该CDR电路能恢复1.25～4.00 Gbps之间的伪随机数据电路,锁定时间为2.1 μs,VCO输出的抖动为47.12 ps.
