A 1.4-2 GHz phase-locked loop （PLL） ∑-△ fraction-N frequency synthesizer with automatic fre- quency control （AFC） for 802.1 lah applications is presented. A class-C voltage control oscillator （VCO） ranging fr...A 1.4-2 GHz phase-locked loop （PLL） ∑-△ fraction-N frequency synthesizer with automatic fre- quency control （AFC） for 802.1 lah applications is presented. A class-C voltage control oscillator （VCO） ranging from 1.4 to 2 GHz is integrated on-chip to save power for the sub-GHz band. A novel AFC algorithm is introduced to maintain the VCO oscillation at the start-up and automatically search for the appropriate control word of the switched-capacitor array to extend the PLL tuning range. A 20-bit third-order ∑-△ modulator is utilized to reduce the fraction spurs while achieving a frequency resolution that is lower than 30 Hz. The measurement results show that the frequency synthesizer has achieved a phase noise of 〈 -120 dBc/Hz at 1 MHz offset and consumes 11.1 mW from a 1.7 V supply. Moreover, compared with the traditional class-A counterparts, the phase noise in class-C mode has been improved by 5 dB under the same power consumption.展开更多
The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoreti...The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL＇s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor （CMOS） technology.展开更多
An improved adaptive frequency calibration（AFC） has been employed to implement a fast lock phaselocked loop based frequency synthesizer in a 0.18μm CMOS process.The AFC can work in two modes：the frequency calibrat...An improved adaptive frequency calibration（AFC） has been employed to implement a fast lock phaselocked loop based frequency synthesizer in a 0.18μm CMOS process.The AFC can work in two modes：the frequency calibration mode and the store/load mode.In the frequency calibration mode,a novel frequency-detector is used to reduce the frequency calibration time to 16 us typically.In the store/load mode,the AFC makes the voltage-controlled oscillator（VCO） return to the calibrated frequency in about 1μs by loading the calibration result stored after the frequency calibration.The experimental results show that the VCO tuning frequency range is about 620-920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is-82 dBc/Hz.The lock time is about 20μs in frequency calibration mode and about 5 us in store/load mode.The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.展开更多
A fast-hopping 3-band （mode 1） multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies ...A fast-hopping 3-band （mode 1） multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 ×1.8 mm^2.展开更多
This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation...This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.展开更多
文摘A 1.4-2 GHz phase-locked loop （PLL） ∑-△ fraction-N frequency synthesizer with automatic fre- quency control （AFC） for 802.1 lah applications is presented. A class-C voltage control oscillator （VCO） ranging from 1.4 to 2 GHz is integrated on-chip to save power for the sub-GHz band. A novel AFC algorithm is introduced to maintain the VCO oscillation at the start-up and automatically search for the appropriate control word of the switched-capacitor array to extend the PLL tuning range. A 20-bit third-order ∑-△ modulator is utilized to reduce the fraction spurs while achieving a frequency resolution that is lower than 30 Hz. The measurement results show that the frequency synthesizer has achieved a phase noise of 〈 -120 dBc/Hz at 1 MHz offset and consumes 11.1 mW from a 1.7 V supply. Moreover, compared with the traditional class-A counterparts, the phase noise in class-C mode has been improved by 5 dB under the same power consumption.
基金supported by the National Natural Science Foundation of China under Grant No. 61006027the New Century Excellent Talents Program of China under Grant No. NCET-10-0297
文摘The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL＇s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor （CMOS） technology.
基金Project supported by the National High Technology Research and Development Program of China(No.2007AA01Z2a8).
文摘An improved adaptive frequency calibration（AFC） has been employed to implement a fast lock phaselocked loop based frequency synthesizer in a 0.18μm CMOS process.The AFC can work in two modes：the frequency calibration mode and the store/load mode.In the frequency calibration mode,a novel frequency-detector is used to reduce the frequency calibration time to 16 us typically.In the store/load mode,the AFC makes the voltage-controlled oscillator（VCO） return to the calibrated frequency in about 1μs by loading the calibration result stored after the frequency calibration.The experimental results show that the VCO tuning frequency range is about 620-920 MHz and the in-band phase noise within the loop bandwidth of 10 kHz is-82 dBc/Hz.The lock time is about 20μs in frequency calibration mode and about 5 us in store/load mode.The synthesizer consumes 12 mA from a single 1.8 V supply voltage when steady.
基金Project supported by the National Natural Science Foundation of China(No.60606009)
文摘A fast-hopping 3-band （mode 1） multi-band orthogonal frequency division multiplexing ultra-wideband frequency synthesizer is presented. This synthesizer uses two phase-locked loops for generating steady frequencies and one quadrature single-sideband mixer for frequency shifting and quadrature frequency generation. The generated carriers can hop among 3432 MHz, 3960 MHz, and 4488 MHz. Implemented in a 0.13 μm CMOS process, this fully integrated synthesizer consumes 27 mA current from a 1.2 V supply. Measurement shows that the out-of-band spurious tones are below -50 dBc, while the in-band spurious tones are below -34 dBc. The measured hopping time is below 2 ns. The core die area is 1.0 ×1.8 mm^2.
基金supported by the National High Technology Research and Development Program of China(No.2011AA040102)
文摘This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.
