针对现有能够应用于太赫兹超高速无线网络的能量和频谱感知的媒介接入控制(energy and spectrum-aware media access control,ES-MAC)及IEEE802.15.3c协议存在的时隙申请量未及时更新、超帧结构不合理及分配时隙时未合并同一对节点之间...针对现有能够应用于太赫兹超高速无线网络的能量和频谱感知的媒介接入控制(energy and spectrum-aware media access control,ES-MAC)及IEEE802.15.3c协议存在的时隙申请量未及时更新、超帧结构不合理及分配时隙时未合并同一对节点之间的时隙请求等问题,提出了一种高吞吐量低时延MAC(high throughput low delay MAC,HLMAC)协议。通过设计一种新的超帧结构,使节点及时得到时隙分配信息,大大降低数据接入时延;通过更新时隙请求量和合并同一对节点的时隙请求,增加了数据发送量,提高了网络吞吐量。理论分析表明了HLMAC协议的有效性,仿真结果显示它比ES-MAC协议增加了65.7%的网络吞吐量,同时降低了30%的接入时延。展开更多
Abstract:A low-delay loop detection algorithm for bit-flipping based iteration LDPC decoding is proposed.By introducing the concept of loop characteristic,only the iteration steps with loop characteristics are detecte...Abstract:A low-delay loop detection algorithm for bit-flipping based iteration LDPC decoding is proposed.By introducing the concept of loop characteristic,only the iteration steps with loop characteristics are detected and labeled for the subsequent loop detection.As a result,computation delay is greatly reduced.Furthermore,the position vector for the selected iteration steps is also established to implement loop detection for these iteration steps,which reduces the hardware cost of the loop detection as well.The validity of the proposed algorithm is verified by simulations.展开更多
文摘针对现有能够应用于太赫兹超高速无线网络的能量和频谱感知的媒介接入控制(energy and spectrum-aware media access control,ES-MAC)及IEEE802.15.3c协议存在的时隙申请量未及时更新、超帧结构不合理及分配时隙时未合并同一对节点之间的时隙请求等问题,提出了一种高吞吐量低时延MAC(high throughput low delay MAC,HLMAC)协议。通过设计一种新的超帧结构,使节点及时得到时隙分配信息,大大降低数据接入时延;通过更新时隙请求量和合并同一对节点的时隙请求,增加了数据发送量,提高了网络吞吐量。理论分析表明了HLMAC协议的有效性,仿真结果显示它比ES-MAC协议增加了65.7%的网络吞吐量,同时降低了30%的接入时延。
基金National Science Foundation of China(No.61072069)the 111 Project(B08038)
文摘Abstract:A low-delay loop detection algorithm for bit-flipping based iteration LDPC decoding is proposed.By introducing the concept of loop characteristic,only the iteration steps with loop characteristics are detected and labeled for the subsequent loop detection.As a result,computation delay is greatly reduced.Furthermore,the position vector for the selected iteration steps is also established to implement loop detection for these iteration steps,which reduces the hardware cost of the loop detection as well.The validity of the proposed algorithm is verified by simulations.
