CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a bri...CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.展开更多
Wind energy systems (WESs) based on doubly-fed induction generators (DFIGs) have enormous potential for meeting the future demands related to clean energy. Due to the low inertia and intermittency of power injection, ...Wind energy systems (WESs) based on doubly-fed induction generators (DFIGs) have enormous potential for meeting the future demands related to clean energy. Due to the low inertia and intermittency of power injection, a WES is equipped with a virtual inertial controller (VIC) to support the system during a frequency deviation event. The frequency deviation measured by a phase locked loop (PLL) installed on a point of common coupling (PCC) bus is the input signal to the VIC. However, a VIC with an improper inertial gain could deteriorate the damping of the power system, which may lead to instability. To address this issue, a mathematical formulation for calculating the synchronizing and damping torque coefficients of a WES-integrated single-machine infinite bus (SMIB) system while considering PLL and VIC dynamics is proposed in this paper. In addition, a power system stabilizer (PSS) is designed for wind energy integrated power systems to enhance electromechanical oscillation damping. A small-signal stability assessment is performed using the infinite bus connected to a synchronous generator of higher-order dynamics integrated with a VIC-equipped WES. Finally, the performance and robustness of the proposed PSS is demonstrated through time-domain simulation in SMIB and nine-bus test systems integrated with WES under several case studies.展开更多
As the proportion of converter-interfaced renewable energy resources in the power system is increasing,the strength of the power grid at the connection point of wind turbine generators(WTGs)is gradually weakening.Exis...As the proportion of converter-interfaced renewable energy resources in the power system is increasing,the strength of the power grid at the connection point of wind turbine generators(WTGs)is gradually weakening.Existing research has shown that when connected with the weak grid,the stability of the traditional grid-following controlled converters will deteriorate,and they are prone to unstable phenomena such as oscillation.Due to the limitations of linear analysis that cannot sufficiently capture the stability phenomena,transient stability must be investigated.So far,standalone time-domain simulations or analytical Lyapunov stability criteria have been used to investigate transient stability.However,the time-domain simulations have proven to be computationally too heavy,while analytical methods are difficult to formulate for larger systems,require many modelling assumptions,and are often conservative in estimating the stability boundary.This paper proposes and demonstrates an innovative approach to estimating the transient stability boundary via combining the linear Lyapunov function and the reverse-time trajectory technique.The proposed methodology eliminates the need of time-consuming simulations and the conservative nature of Lyapunov functions.This study brings out the clear distinction between the stability boundaries with different post-fault active current ramp rate controls.At the same time,it provides a new perspective on critical clearing time for wind turbine systems.The stability boundary is verified using time-domain simulation studies.展开更多
Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a vol...Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.展开更多
In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has b...In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.展开更多
This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objec...This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.展开更多
Loss of synchronization is one of the main issues for a grid-feeding converter in a weak grid after being subjected to a large disturbance.The synchronous transient is highly nonlinear due to phase movement and freque...Loss of synchronization is one of the main issues for a grid-feeding converter in a weak grid after being subjected to a large disturbance.The synchronous transient is highly nonlinear due to phase movement and frequency limiters.However,none of the previous research has considered the anti-windup PI in the phase-locked loop,which is commonly implemented in reality and introduced as an additional nonlinear transient.This work provides a taxonomy to evaluate and compare the effect of different anti-windup PI limiters on synchronization stability,including clamping,back-calculation and combined method.Different anti-windup PI limiters allocate zeros and poles differently and have different impacts on damping and stability enhancement.A case study implemented in Matlab/Simulink serves to compare the trajectory of the converter phase and frequency using different anti-windup PI in the scenario of both with and without equilibrium points during the fault.Simulation results show that anti-windup PI limiters increase damping during the fault and thus improve the synchronization stability margin.展开更多
The dynamic coupling effect,which is introduced by the dual-sequence phase-locked loops(PLLs)used in doublyfed induction generator(DFIG)based wind energy generation systems(WEGSs)during asymmetric low voltage ride-thr...The dynamic coupling effect,which is introduced by the dual-sequence phase-locked loops(PLLs)used in doublyfed induction generator(DFIG)based wind energy generation systems(WEGSs)during asymmetric low voltage ride-through(LVRT)in weak grid,needs attention.In order to study this new dynamic coupling effect,an equivalent two-degree-of-freedom(2-DOF)spring damper particle model is used in this paper to develop a small-signal model for the dual-sequence PLLs.The dynamic interaction between the positive-sequence(PS)and negative-sequence(NS)PLLs is unveiled.Moreover,the impact of the dynamic coupling between the dual-sequence PLLs on the dynamic stability during the steady-state stage of an asymmetric fault is analyzed.The analysis results show that the dynamic coupling between the dual-sequence PLLs will cause drift in the frequency and damping for the PS and NS PLL modes.This will change the instability modal of the system and introduce the risk of dynamic instability.Hence,the effectiveness of existing control strategies for enhancing the dynamic stability will be decreased.Finally,a novel PLL structure is designed to improve the dynamic stability of the system during the steady-state stage of an asymmetric fault.The effectiveness of the proposed strategy is verified by simulations and experiments.展开更多
The doubly-fed induction generator(DFIG)is considered to provide a low-reactance path in the negative-sequence system and naturally comply with requirements on the negative-sequence reactive current in emerging grid c...The doubly-fed induction generator(DFIG)is considered to provide a low-reactance path in the negative-sequence system and naturally comply with requirements on the negative-sequence reactive current in emerging grid codes.This paper shows otherwise and how the control strategy of converters plays a key role in the formation of the active and reactive current components.After investigating the existing control strategies from the perspective of grid code compliance and showing how they fail in addressing emerging requirements on the negative-sequence reactive current,we propose a new coordinated control strategy that complies with reactive current requirements in grid codes in the positive-and negative-sequence systems.The proposed method fully takes advantage of the current and voltage capacities of both the rotor-side converter(RSC)and grid-side converter(GSC),which enables the grid code compliance of the DFIG under unbalanced three-phase voltages due to asymmetrical faults.The mathematical investigations and proposed strategy are validated with detailed simulation models using the Electric Power Research Institute(EPRI)benchmark system.The derived mathematical expressions provide analytical clarifications on the response of the DFIG in the negative-sequence system from the grid perspective.展开更多
This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation...This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.展开更多
Single-event transient susceptibility of phase-locked loops has been investigated. The charge pump is the most sensitive component of the PLL to SET, and it is hard to mitigate this effect at the transistor level. A t...Single-event transient susceptibility of phase-locked loops has been investigated. The charge pump is the most sensitive component of the PLL to SET, and it is hard to mitigate this effect at the transistor level. A test circuit was designed on a 65 nm process using a new system-level radiation-hardening-by-design technique.Heavy-ion testing was used to evaluate the radiation hardness. Analyses and discussion of the feasibility of this method are also presented.展开更多
A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed t...A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.展开更多
Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the proble...Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns.展开更多
基金supported by the Pioneer Hundred Talents Program,Chinese Academy of Sciences.
文摘CMOS analog and mixed-signal phase-locked loops(PLL)are widely used in varies of the system-on-chips(SoC)as the clock generator or frequency synthesizer.This paper presents an overview of the AMS-PLL,including:1)a brief introduction of the basics of the charge-pump based PLL,which is the most widely used AMS-PLL architecture due to its simplicity and robustness;2)a summary of the design issues of the basic CPPLL architecture;3)a systematic introduction of the techniques for the performance enhancement of the CPPLL;4)a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter(<100 fs)with lower power consumption compared with the CPPLL,including the injection-locked PLL(ILPLL),subsampling(SSPLL)and sampling PLL(SPLL);5)a discussion about the consideration of the AMS-PLL architecture selection,which could help designers meet their performance requirements.
文摘Wind energy systems (WESs) based on doubly-fed induction generators (DFIGs) have enormous potential for meeting the future demands related to clean energy. Due to the low inertia and intermittency of power injection, a WES is equipped with a virtual inertial controller (VIC) to support the system during a frequency deviation event. The frequency deviation measured by a phase locked loop (PLL) installed on a point of common coupling (PCC) bus is the input signal to the VIC. However, a VIC with an improper inertial gain could deteriorate the damping of the power system, which may lead to instability. To address this issue, a mathematical formulation for calculating the synchronizing and damping torque coefficients of a WES-integrated single-machine infinite bus (SMIB) system while considering PLL and VIC dynamics is proposed in this paper. In addition, a power system stabilizer (PSS) is designed for wind energy integrated power systems to enhance electromechanical oscillation damping. A small-signal stability assessment is performed using the infinite bus connected to a synchronous generator of higher-order dynamics integrated with a VIC-equipped WES. Finally, the performance and robustness of the proposed PSS is demonstrated through time-domain simulation in SMIB and nine-bus test systems integrated with WES under several case studies.
文摘As the proportion of converter-interfaced renewable energy resources in the power system is increasing,the strength of the power grid at the connection point of wind turbine generators(WTGs)is gradually weakening.Existing research has shown that when connected with the weak grid,the stability of the traditional grid-following controlled converters will deteriorate,and they are prone to unstable phenomena such as oscillation.Due to the limitations of linear analysis that cannot sufficiently capture the stability phenomena,transient stability must be investigated.So far,standalone time-domain simulations or analytical Lyapunov stability criteria have been used to investigate transient stability.However,the time-domain simulations have proven to be computationally too heavy,while analytical methods are difficult to formulate for larger systems,require many modelling assumptions,and are often conservative in estimating the stability boundary.This paper proposes and demonstrates an innovative approach to estimating the transient stability boundary via combining the linear Lyapunov function and the reverse-time trajectory technique.The proposed methodology eliminates the need of time-consuming simulations and the conservative nature of Lyapunov functions.This study brings out the clear distinction between the stability boundaries with different post-fault active current ramp rate controls.At the same time,it provides a new perspective on critical clearing time for wind turbine systems.The stability boundary is verified using time-domain simulation studies.
基金supported by the National Natural Science Foundation of China(No.51677142)the National Key R&D Program of China(No.2016YFB0900600)。
文摘Voltage source converter based high-voltage direct current(VSC-HVDC)transmission technology has been extensively employed in power systems with a high penetration of renewable energy resources.However,connecting a voltage source converter(VSC)to an AC weak grid may cause the converter system to become unstable.In this paper,a phase-shift phaselocked loop(PS-PLL)is proposed wherein a back electromotive force(BEMF)observer is added to the conventional phaselocked loop(PLL).The BEMF observer is used to observe the voltage of the infinite grid in the stationaryαβframe,which avoids the problem of inaccurate observations of the grid voltage in the dq frame that are caused by the output phase angle errors of the PLL.The VSC using the PS-PLL can operate as if it is facing a strong grid,thus enhancing the stability of the VSC-HVDC system.The proposed PS-PLL only needs to be properly modified on the basis of a traditional PLL,which makes it easy to implement.In addition,because it is difficult to obtain the exact impedance of the grid,the influence of shortcircuit ratio(SCR)estimation errors on the performance of the PS-PLL is also studied.The effectiveness of the proposed PSPLL is verified by the small-signal stability analysis and timedomain simulation.
基金This work is supported in part by the National Natural Science Foundation of China(No.51807089,51877104)in part by the Natural Science Foundation of Jiangsu Province(No.BK20180432).
文摘In renewable power generation systems,ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters.Nowadays,the phase-locked loop(PLL)technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions.Even though a lot of PLLs have been proposed,an overview and comparative analysis of multiple PLLs can be helpful for practical applications.In addition,the weak grid condition is a great challenge for the system.Therefore,this study first presents an overview of the existing PLLs together with their general structures and basic working principles.Depending on the implementation of the phase detector,the PLL can be divided into three categories:power-based PLL(pPLL),orthogonal-signalgenerator-based PLL(OSG-PLL)and adaptive-filter-based PLL(AF-PLL).Then,from the above classification,seven typical single-phase PLLs are selected for further study.Finally,some test results are given,and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.
基金supported by the National Natural Science Foundation of China under Grant 62004028,62090041the Science Foundation of Sichuan under Grant 2022NSFSC0927.
文摘This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator(VCO)-based phase-locked loops(PLLs)for clock generation in different applications.Partic-ularly,the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power,jitter and area.An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analyt-ically and benchmarked with respect to their figure-of-merit(FoM).The paper also summarizes the key concerns on the selection of dif-ferent circuit techniques to optimize the clock performance under dif-ferent scenarios.
基金supported in part by the National Natural Science Foundation of China(U2166601,U2066602)the Science and Technology Department of Xinjiang under Grant No.2021D01C086funded by Sustainable Energy Authority of Ireland(SEAI)by under project FRESLIPS,Grant No.RDD/00681.
文摘Loss of synchronization is one of the main issues for a grid-feeding converter in a weak grid after being subjected to a large disturbance.The synchronous transient is highly nonlinear due to phase movement and frequency limiters.However,none of the previous research has considered the anti-windup PI in the phase-locked loop,which is commonly implemented in reality and introduced as an additional nonlinear transient.This work provides a taxonomy to evaluate and compare the effect of different anti-windup PI limiters on synchronization stability,including clamping,back-calculation and combined method.Different anti-windup PI limiters allocate zeros and poles differently and have different impacts on damping and stability enhancement.A case study implemented in Matlab/Simulink serves to compare the trajectory of the converter phase and frequency using different anti-windup PI in the scenario of both with and without equilibrium points during the fault.Simulation results show that anti-windup PI limiters increase damping during the fault and thus improve the synchronization stability margin.
基金supported in part by the National Natural Science Foundation of China(NSFC)(No.51977019)the Joint Research Fund in Smart Grid(No.U1966208)under a cooperative agreement between the NSFC and State Grid Corporation of China(SGCC)。
文摘The dynamic coupling effect,which is introduced by the dual-sequence phase-locked loops(PLLs)used in doublyfed induction generator(DFIG)based wind energy generation systems(WEGSs)during asymmetric low voltage ride-through(LVRT)in weak grid,needs attention.In order to study this new dynamic coupling effect,an equivalent two-degree-of-freedom(2-DOF)spring damper particle model is used in this paper to develop a small-signal model for the dual-sequence PLLs.The dynamic interaction between the positive-sequence(PS)and negative-sequence(NS)PLLs is unveiled.Moreover,the impact of the dynamic coupling between the dual-sequence PLLs on the dynamic stability during the steady-state stage of an asymmetric fault is analyzed.The analysis results show that the dynamic coupling between the dual-sequence PLLs will cause drift in the frequency and damping for the PS and NS PLL modes.This will change the instability modal of the system and introduce the risk of dynamic instability.Hence,the effectiveness of existing control strategies for enhancing the dynamic stability will be decreased.Finally,a novel PLL structure is designed to improve the dynamic stability of the system during the steady-state stage of an asymmetric fault.The effectiveness of the proposed strategy is verified by simulations and experiments.
文摘The doubly-fed induction generator(DFIG)is considered to provide a low-reactance path in the negative-sequence system and naturally comply with requirements on the negative-sequence reactive current in emerging grid codes.This paper shows otherwise and how the control strategy of converters plays a key role in the formation of the active and reactive current components.After investigating the existing control strategies from the perspective of grid code compliance and showing how they fail in addressing emerging requirements on the negative-sequence reactive current,we propose a new coordinated control strategy that complies with reactive current requirements in grid codes in the positive-and negative-sequence systems.The proposed method fully takes advantage of the current and voltage capacities of both the rotor-side converter(RSC)and grid-side converter(GSC),which enables the grid code compliance of the DFIG under unbalanced three-phase voltages due to asymmetrical faults.The mathematical investigations and proposed strategy are validated with detailed simulation models using the Electric Power Research Institute(EPRI)benchmark system.The derived mathematical expressions provide analytical clarifications on the response of the DFIG in the negative-sequence system from the grid perspective.
基金supported by the National High Technology Research and Development Program of China(No.2011AA040102)
文摘This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.
文摘Single-event transient susceptibility of phase-locked loops has been investigated. The charge pump is the most sensitive component of the PLL to SET, and it is hard to mitigate this effect at the transistor level. A test circuit was designed on a 65 nm process using a new system-level radiation-hardening-by-design technique.Heavy-ion testing was used to evaluate the radiation hardness. Analyses and discussion of the feasibility of this method are also presented.
文摘A high-speed dual-modulus divide-by-32/33 prescaler has been developed using 0.25 μm CMOS technology. The source-coupled logic (SCL) structure is used to reduce the switching noise and to ameliorate the power-speed tradeoff. The proposed prescaler can operate at high frequency with a low-power consumption. Based on the 2.5 V, 0.25 μm CMOS model, simulation results indicate that the maximum input frequency of the prescaler is up to 3.2 GHz. Running at 2.5 V, the circuit consumes only 4.6 mA at an input frequency 2.5 GHz.
基金National Key Research and Development Program of China(No.2018YFE0208200)National Natural Science Foundation of China(Nos.61971307,61905175,51775377)+5 种基金National Key Research and Development Plan Project(No.2020YFB2010800)The Fok Ying Tung Education Foundation(No.171055)China Postdoctoral Science Foundation(No.2020M680878)Guangdong Province Key Research and Development Plan Project(No.2020B0404030001)Tianjin Science and Technology Plan Project(No.20YDTPJC01660)Project of Foreign Affairs Committee of China Aviation Development Sichuan Gas Turbine Research Institute(Nos.GJCZ-2020-0040,GJCZ-2020-0041)。
文摘Synchronous sampling is very essential in underwater multilinear array seismic exploration system in which every acquisition node(AN)samples analog signals by its own analog-digital converter(ADC).Aiming at the problems of complex synchronous sampling method and long locking time after varying sampling rate in traditional underwater seismic exploration system,an improved synchronous sampling model based on the master-slave synchronous model and local clock asynchronous drive with non phase locked loop(PLL)is built,and a high-precision synchronous sampling method is proposed,which combines the short-term stability of local asynchronous driving clock with the master-slave synchronous calibration of local sampling clock.Based on the improved synchronous sampling model,the influence of clock stability,transmission delay and phase jitter on synchronous sampling error is analyzed,and a high-precision calibration method of synchronous sampling error based on step-by-step compensation of transmission delay is proposed.The model and method effectively realize the immunity of phase jitter on synchronous sampling error in principle,and compensate the influence of signal transmission delay on synchronous sampling error.At the same time,it greatly reduces the complexity of software and hardware implementation of synchronous sampling,and solves the problem of long locking time after changing the sampling rate in traditional methods.The experimental system of synchronous sampling for dual linear array is built,and the synchronous sampling accuracy is better than 5 ns.
