A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge...A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.展开更多
We perform a theoretical study of the effects of the lightly doped drain （LDD） and high-k dielectric on the performances of double gate p-i-n tunneling graphene nanoribbon field effect transistors （TFETs）. The mod...We perform a theoretical study of the effects of the lightly doped drain （LDD） and high-k dielectric on the performances of double gate p-i-n tunneling graphene nanoribbon field effect transistors （TFETs）. The models are based on non-equilibrium Green＇s functions （NEGF） solved self-consistently with 3D-Poisson＇s equations. For the first time, hetero gate dielectric and single LDD TFETs （SL-HTFETs） are proposed and investigated. Simulation results show SL-HTFETs can effectively decrease leakage current, sub-threshold swing, and increase on-off current ratio compared to conventional TFETs and Si-based devices; the SL-HTFETs from the 3p ＋ 1 family have better switching characteristics than those from the 3p family due to smaller effective masses of the former. In addition, comparison of scaled performances between SL-HTFETs and conventional TFETs show that SL-HTFETs have better scaling properties than the conventional TFETs, and thus could be promising devices for logic and ultra-low power applications.展开更多
An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented...An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.展开更多
The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain （LDD） nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injectio...The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain （LDD） nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injections, i.e. low gate voltage hot hole injection （LGVHHI）, gate-induced drain leakage induced hot-hole injection （GIDLIHHI） and substrate hot-hole injection （SHHI）, have different influences on the devices damaged already by the previous hot electron injection （HEI） because of the different locations of trapping holes and interface states induced by the three types of injections, i.e. three types of stresses. Experimental results show that GIDLIHHI and LGVHHI cannot recover the degradation of electron trapping, but SHHI can. Although SHHI can recover the device＇s performance, the recovery is slight and reaches saturation quickly, which is suggested here to be attributed to the fact that trapped holes are too few and the equilibrium is reached between the trapping and releasing of holes which can be set up quickly in the ultrathin oxide.展开更多
The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress...The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV （Vg = Vth） stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage （GIDL） current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Yg = Yth with various drain biases. Experimental results show that the degradation slopes （n） range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET （0.5 - 0.6） and also that of the long gate length LDD MOSFET （- 0.8）.展开更多
Improving solar cell performance by increasing solar cell efficiency by various process optimization had always been a simple straight-forward methodology followed in a R&D or in a solar cell manufacturing company...Improving solar cell performance by increasing solar cell efficiency by various process optimization had always been a simple straight-forward methodology followed in a R&D or in a solar cell manufacturing company. This is also the most cost-effective practice to improve a product performance using the same technology without the need to procure alternative or expensive raw materials or by adopting advanced solar cell processing techniques. Aluminium Back Surface Field (Al-BSF) technology using multi-crystalline wafers (mc-Si) had been a well-established and a dominant product in the solar industry for more than two decades. However, as the industry progresses, the demand for high efficiency solar cells and modules started going up and full area Aluminium BSF based cells suffers from a lot of inherent limitations on cell efficiency. This is primarily due to the intrinsic high density of crystal lattice defects or otherwise called as grain boundary defects present dominantly only in mc-Si wafers. These grain boundaries tends to accumulate several defects and become trap centres which cause high recombination for minority carriers thereby exhibiting lower conversion efficiency and higher dispersion in electrical parameters in batches of tested cells. Years of research using this material have helped to derive the maximum benefits using this mc-Si wafer in producing industrial full area BSF cells and we can say with certainty that the efficiency potential has reached the saturation point with this technology. An interesting development that happened in the area of improving the final product performance using mc-Si wafers at both cell and module level, is by replacing the conventional acid texturing process with an introduction of a nano-texturing process called Metal Catalysed Chemical Etching (MCCE) using specialized chemicals which improves the light trapping capabilities by creation of inverted pyramid texture on the silicon wafer surface and thereby enabling the wafers to absorb sunlight over a broader range of展开更多
基金supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2010ZX02201)the National Natural Science Foundation of China (Grant No. 61176069)the National Defense Pre-Research of China (Grant No. 51308020304)
文摘A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.
文摘We perform a theoretical study of the effects of the lightly doped drain （LDD） and high-k dielectric on the performances of double gate p-i-n tunneling graphene nanoribbon field effect transistors （TFETs）. The models are based on non-equilibrium Green＇s functions （NEGF） solved self-consistently with 3D-Poisson＇s equations. For the first time, hetero gate dielectric and single LDD TFETs （SL-HTFETs） are proposed and investigated. Simulation results show SL-HTFETs can effectively decrease leakage current, sub-threshold swing, and increase on-off current ratio compared to conventional TFETs and Si-based devices; the SL-HTFETs from the 3p ＋ 1 family have better switching characteristics than those from the 3p family due to smaller effective masses of the former. In addition, comparison of scaled performances between SL-HTFETs and conventional TFETs show that SL-HTFETs have better scaling properties than the conventional TFETs, and thus could be promising devices for logic and ultra-low power applications.
文摘An analytical model for the channel potential and the threshold voltage of the short channel dual-material-gate lightly doped drain （DMG-LDD） metal-oxide-semiconductor field-effect transistor （MOSFET） is presented using the parabolic approximation method. The proposed model takes into account the effects of the LDD region length, the LDD region doping, the lengths of the gate materials and their respective work functions, along with all the major geometrical parameters of the MOSFET. The impact of the LDD region length, the LDD region doping, and the channel length on the channel potential is studied in detail. Furthermore, the threshold voltage of the device is calculated using the minimum middle channel potential, and the result obtained is compared with the DMG MOSFET threshold voltage to show the improvement in the threshold voltage roll-off. It is shown that the DMG-LDD MOSFET structure alleviates the problem of short channel effects （SCEs） and the drain induced barrier lowering （DIBL） more efficiently. The proposed model is verified by comparing the theoretical results with the simulated data obtained by using the commercially available ATLASTM 2D device simulator.
文摘The behaviours of three types of hot-hole injections in ultrashort channel lightly doped drain （LDD） nMOSFETs with ultrathin oxide under an alternating stress have been compared. The three types of hot-hole injections, i.e. low gate voltage hot hole injection （LGVHHI）, gate-induced drain leakage induced hot-hole injection （GIDLIHHI） and substrate hot-hole injection （SHHI）, have different influences on the devices damaged already by the previous hot electron injection （HEI） because of the different locations of trapping holes and interface states induced by the three types of injections, i.e. three types of stresses. Experimental results show that GIDLIHHI and LGVHHI cannot recover the degradation of electron trapping, but SHHI can. Although SHHI can recover the device＇s performance, the recovery is slight and reaches saturation quickly, which is suggested here to be attributed to the fact that trapped holes are too few and the equilibrium is reached between the trapping and releasing of holes which can be set up quickly in the ultrathin oxide.
基金Project supported by the National High Technology Research and Development Program of China （Grant No 2003AA1Z1630） and the National Natural Science Foundation of China （Grant No 60376024）.
文摘The hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide under the low gate voltage （LGV） （at Vg = Vth, where Yth is the threshold voltage） stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV （Vg = Vth） stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage （GIDL） current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90 nm gate length LDD-NMOSFET with 1.4 nm gate oxide under the LGV stress at Yg = Yth with various drain biases. Experimental results show that the degradation slopes （n） range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET （0.5 - 0.6） and also that of the long gate length LDD MOSFET （- 0.8）.
文摘Improving solar cell performance by increasing solar cell efficiency by various process optimization had always been a simple straight-forward methodology followed in a R&D or in a solar cell manufacturing company. This is also the most cost-effective practice to improve a product performance using the same technology without the need to procure alternative or expensive raw materials or by adopting advanced solar cell processing techniques. Aluminium Back Surface Field (Al-BSF) technology using multi-crystalline wafers (mc-Si) had been a well-established and a dominant product in the solar industry for more than two decades. However, as the industry progresses, the demand for high efficiency solar cells and modules started going up and full area Aluminium BSF based cells suffers from a lot of inherent limitations on cell efficiency. This is primarily due to the intrinsic high density of crystal lattice defects or otherwise called as grain boundary defects present dominantly only in mc-Si wafers. These grain boundaries tends to accumulate several defects and become trap centres which cause high recombination for minority carriers thereby exhibiting lower conversion efficiency and higher dispersion in electrical parameters in batches of tested cells. Years of research using this material have helped to derive the maximum benefits using this mc-Si wafer in producing industrial full area BSF cells and we can say with certainty that the efficiency potential has reached the saturation point with this technology. An interesting development that happened in the area of improving the final product performance using mc-Si wafers at both cell and module level, is by replacing the conventional acid texturing process with an introduction of a nano-texturing process called Metal Catalysed Chemical Etching (MCCE) using specialized chemicals which improves the light trapping capabilities by creation of inverted pyramid texture on the silicon wafer surface and thereby enabling the wafers to absorb sunlight over a broader range of
