A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs o...A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8′8 block. The proposed architecture works in a parallel way and is simulated by Modelsim 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 Field Programmable Gate Array(FPGA) device, and verified by hardware platform. The implementation results show that this architecture can achieve 190 MHz and 11 clock cycles are reduced to complete the entire interpolation process in comparison with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.展开更多
A minimum distortion direction prediction-based novel fast half-pixel motion vector search algorithm is proposed, which can reduce considerably the computation load of half-pixel search. Based on the single valley cha...A minimum distortion direction prediction-based novel fast half-pixel motion vector search algorithm is proposed, which can reduce considerably the computation load of half-pixel search. Based on the single valley characteristic of half-pixel error matching function inside search grid, the minimum distortion direction is predicted with the help of comparative results of sum of absolute difference(SAD) values of four integer-pixel points around integer-pixel motion vector. The experimental results reveal that, to all kinds of video sequences, the proposed algorithm can obtain almost the same video quality as that of the half-pixel full search algorithm with a decrease of computation cost by more than 66%.展开更多
In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented alg...In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8x8 block. The proposed architecture works in a parallel way and is simulated by Modelsirn 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 FPGA device. The implementation results show that this architecture can achieve 190 MHz and 10 clock cycles are reduced to complete the entire interpolation process when compared with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.展开更多
在视频编码系统中,半像素精度的运动估计虽可以明显地改善编码效果,但也因此增加了不少运算量。为了降低运算量和提高半像素运动估计的速度,提出了一种全新的半像素搜索算法(half-pixel motion estimation based on linear prediction,...在视频编码系统中,半像素精度的运动估计虽可以明显地改善编码效果,但也因此增加了不少运算量。为了降低运算量和提高半像素运动估计的速度,提出了一种全新的半像素搜索算法(half-pixel motion estimation based on linear prediction,简称BLPHME),其关键思想是通过分析整像素搜索和半像素搜索结果之间的相关性来建立一个线性模型,通过动态调整判决门限,以便预测并跳过那些不能从半像素块匹配搜索中得到好处的块。实验结果表明,该算法不仅可以明显地降低运动估计的运算量,同时还能得到与传统算法非常接近的图像质量和码率。此外,该算法还可以和基于整像素和半像素的快速运动估计算法一起使用,以进一步降低运算量。展开更多
文摘A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8′8 block. The proposed architecture works in a parallel way and is simulated by Modelsim 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 Field Programmable Gate Array(FPGA) device, and verified by hardware platform. The implementation results show that this architecture can achieve 190 MHz and 11 clock cycles are reduced to complete the entire interpolation process in comparison with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.
文摘A minimum distortion direction prediction-based novel fast half-pixel motion vector search algorithm is proposed, which can reduce considerably the computation load of half-pixel search. Based on the single valley characteristic of half-pixel error matching function inside search grid, the minimum distortion direction is predicted with the help of comparative results of sum of absolute difference(SAD) values of four integer-pixel points around integer-pixel motion vector. The experimental results reveal that, to all kinds of video sequences, the proposed algorithm can obtain almost the same video quality as that of the half-pixel full search algorithm with a decrease of computation cost by more than 66%.
文摘In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8x8 block. The proposed architecture works in a parallel way and is simulated by Modelsirn 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 FPGA device. The implementation results show that this architecture can achieve 190 MHz and 10 clock cycles are reduced to complete the entire interpolation process when compared with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.
文摘在视频编码系统中,半像素精度的运动估计虽可以明显地改善编码效果,但也因此增加了不少运算量。为了降低运算量和提高半像素运动估计的速度,提出了一种全新的半像素搜索算法(half-pixel motion estimation based on linear prediction,简称BLPHME),其关键思想是通过分析整像素搜索和半像素搜索结果之间的相关性来建立一个线性模型,通过动态调整判决门限,以便预测并跳过那些不能从半像素块匹配搜索中得到好处的块。实验结果表明,该算法不仅可以明显地降低运动估计的运算量,同时还能得到与传统算法非常接近的图像质量和码率。此外,该算法还可以和基于整像素和半像素的快速运动估计算法一起使用,以进一步降低运算量。
