This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with ...This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.展开更多
设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态...设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度,并降低了系统功耗.通过对版图面积的优化设计,满足了CMOS图像传感器对芯片面积的要求.本设计基于180nm CMOS工艺,仿真结果显示电路实现了60.37dB的信噪失真比(SNDR)和76.37dB的无杂散动态范围(SFDR),有效精度(ENOB)达到了9.74bit.ADC的核心面积仅为140μmⅹ280μm,约为0.04mm2.在2.8V电压下,功耗为9.8mW.展开更多
设计了一种高性能低功耗的10 bit 100 MS/s逐次逼近寄存器（SAR）模数转换器（ADC）.基于优值（FOM）设计了一种数模转换器（DAC）单元电容确定法,从而实现了ADC性能和功耗之间的最优折中,得到了最小的后仿真优值为17.92 f J/步,以及与...设计了一种高性能低功耗的10 bit 100 MS/s逐次逼近寄存器（SAR）模数转换器（ADC）.基于优值（FOM）设计了一种数模转换器（DAC）单元电容确定法,从而实现了ADC性能和功耗之间的最优折中,得到了最小的后仿真优值为17.92 f J/步,以及与之对应的最优单元电容值1.59 f F.为了减小输入共模电压变化引起的信号敏感性失调,设计了改进的P型输入动态预放大锁存比较器,比较器采用共源共栅结构（cascode）作为P型预放大器的偏置,从而增加了预放大器的共模抑制比（CMRR）.模数转换器采用1层多晶硅8层金属（1P8M）55 nm互补型金属氧化物半导体（CMOS）工艺进行了流片验证,在1.3 V电压和100 MS/s采样率的环境下进行测试,信噪失真比（SNDR）的值为59.8 d B,功耗为1.67 mW,有效电路面积仅为0.016 2 mm^2.展开更多
基金supported by the National Natural Science Foundation of China(Nos.61161003,61264001,61166004)the Guangxi Key Laboratory of Precision Navigation Technology and Application Foundation(No.DH201501)
文摘This paper presents a low power 8-bit 1 MS/s SAR ADC with 7.72-bit ENOB. Without an op-amp, an improved segmented capacitor DAC is proposed to reduce the capacitance and the chip area. A dynamic latch comparator with output offset voltage storage technology is used to improve the precision. Adding an extra positive feedback in the latch is to increase the speed. What is more, two pairs of CMOS switches are utilized to eliminate the kickback noise introduced by the latch. The proposed SAR ADC was fabricated in SMIC 0.18μm CMOS technology. The measured results show that this design achieves an SFDR of 61.8 dB and an ENOB of 7.72 bits, and it consumes 67.5μW with the FOM of 312 fJ/conversion-step at 1 MS/s sample under 1.8 V power supply.
文摘设计实现一种应用于CMOS图像传感器的10bit模数转换器(ADC),采用基于逐次逼近的新型流水线结构(Pipelined SAR ADC).提出了一种优化选取其中高精度倍增数模转换器(MDAC)和单位电容值的解析方法.通过采用第一级高精度、半增益MDAC和动态比较器等技术提高了整体电路的线性度,并降低了系统功耗.通过对版图面积的优化设计,满足了CMOS图像传感器对芯片面积的要求.本设计基于180nm CMOS工艺,仿真结果显示电路实现了60.37dB的信噪失真比(SNDR)和76.37dB的无杂散动态范围(SFDR),有效精度(ENOB)达到了9.74bit.ADC的核心面积仅为140μmⅹ280μm,约为0.04mm2.在2.8V电压下,功耗为9.8mW.
文摘设计了一种高性能低功耗的10 bit 100 MS/s逐次逼近寄存器（SAR）模数转换器（ADC）.基于优值（FOM）设计了一种数模转换器（DAC）单元电容确定法,从而实现了ADC性能和功耗之间的最优折中,得到了最小的后仿真优值为17.92 f J/步,以及与之对应的最优单元电容值1.59 f F.为了减小输入共模电压变化引起的信号敏感性失调,设计了改进的P型输入动态预放大锁存比较器,比较器采用共源共栅结构（cascode）作为P型预放大器的偏置,从而增加了预放大器的共模抑制比（CMRR）.模数转换器采用1层多晶硅8层金属（1P8M）55 nm互补型金属氧化物半导体（CMOS）工艺进行了流片验证,在1.3 V电压和100 MS/s采样率的环境下进行测试,信噪失真比（SNDR）的值为59.8 d B,功耗为1.67 mW,有效电路面积仅为0.016 2 mm^2.
