With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provid...With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.展开更多
A path-based timing optimization algorithm for buffer insertion and simultaneous sizing is proposed. Firstly, candidate buffer insertion location and buffer size for each branch in a given routing path were obtained v...A path-based timing optimization algorithm for buffer insertion and simultaneous sizing is proposed. Firstly, candidate buffer insertion location and buffer size for each branch in a given routing path were obtained via localized timing optimization. Then, through evaluating each potential insertion against design objectives, potential optimal buffer insertion locations and sizes for the whole routing tree were determined. At last, by removing redundant buffer insertion operations which do not maximize S （ so ）, given timing requirements are finally fulfilled through minimum number of buffers.展开更多
文摘With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.
文摘A path-based timing optimization algorithm for buffer insertion and simultaneous sizing is proposed. Firstly, candidate buffer insertion location and buffer size for each branch in a given routing path were obtained via localized timing optimization. Then, through evaluating each potential insertion against design objectives, potential optimal buffer insertion locations and sizes for the whole routing tree were determined. At last, by removing redundant buffer insertion operations which do not maximize S （ so ）, given timing requirements are finally fulfilled through minimum number of buffers.
