摘要
A path-based timing optimization algorithm for buffer insertion and simultaneous sizing is proposed. Firstly, candidate buffer insertion location and buffer size for each branch in a given routing path were obtained via localized timing optimization. Then, through evaluating each potential insertion against design objectives, potential optimal buffer insertion locations and sizes for the whole routing tree were determined. At last, by removing redundant buffer insertion operations which do not maximize S （ so ）, given timing requirements are finally fulfilled through minimum number of buffers.
