In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improv...In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.展开更多
In this, today’s world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal...In this, today’s world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal. In any processor, the performance of the system is based on the speed of the multiplier unit involved in its operation. Since multiplier forms the indispensable building blocks of the FIR filter system. Its performance has contributed in determining the execution of the FIR filter system. Also, due to the tremendous development in the technology, many approaches such as an array, Vedic methods are made to speed up the multiplier computations. The problem in speed-up operation and resource utilization of hardware with all the conventional methods due to the critical path found in partial products has to be optimized using proposed method. This paper presents the implementation and execution of a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam, and array multipliers. The FIR filter is simulated for analyzing delay;area and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR filter design utilizing proposed multiplier offers delay around 18.99 and only 4% of LUT slice utilization compared to existing methods. This architecture is coded in VHDL, simulated using the ModelSim and synthesized with Xilinx.展开更多
Decimal multipliers play an important role in our day to day life for commercial, financial and tax applications. Every processor multiplier acts as the basic building block which decides the performance of processor....Decimal multipliers play an important role in our day to day life for commercial, financial and tax applications. Every processor multiplier acts as the basic building block which decides the performance of processor. Time and again research is going on to design high-performance, low-latency BCD multiplier architectures. This paper proposes a new approach to BCD multiplication using vinculum number system. The key feature of the proposed architecture uses entirely a new one digit ROM based BCD multiplier that uses vinculum numbers as operands. Using this one digit BCD multiplier, an N digit BCD multiplier is built by using the vedic vertical cross wire method (Urdhav Triyagbhyam). We have also used our proposed multi operand VBCD Adder (Vinculum BCD Adder) [my paper 26] to add the partial products. In this paper, we show that this approach is a promising alternative to conventional BCD multiplication or other decimal multiplication methods that use alternative decimal representations like 5211, 4221, Xs3 etc.展开更多
The Vedic multiplication algorithm is a very fast way of oral calculation. However, the basis of the algorithm is not available so far. The present paper demystifies the general Vedic algorithm for multiplication by e...The Vedic multiplication algorithm is a very fast way of oral calculation. However, the basis of the algorithm is not available so far. The present paper demystifies the general Vedic algorithm for multiplication by establishment of foundation of the Vedic algorithm of product finding through end results of conventional multiplication. This novel approach, i.e., finding algorithm from the end results of conventional calculations may be useful in devising algorithms similar to Vedic in cases of other calculations. Though the availability of cheap calculators made the Vedic Method obsolete, the present trend resurrected Vedic algorithms by their use in the design of computer processors for enhancing speed and performance.展开更多
Novel high speed energy efficient square root architecture has been reported in this paper. In this architecture, we have blended ancient Indian Vedic mathematics and Bakhshali mathematics to achieve a significant amo...Novel high speed energy efficient square root architecture has been reported in this paper. In this architecture, we have blended ancient Indian Vedic mathematics and Bakhshali mathematics to achieve a significant amount of accuracy in performing the square root operation. Basically, Vedic Duplex method and iterative division method reported in Bakhshali Manuscript have been utilized for that computation. The proposed technique has been compared with the well known Newton-Raphson’s (N-R) technique for square root computation. The algorithm has been implemented and tested using Modelsim simulator, and performance parameters such as the number of lookup tables, propagation delay and power consumption have been estimated using Xilinx ISE simulator. The functionality of the circuitry has been checked using Xilinx Virtex-5 FPGA board.展开更多
The ephemeral Ghaggar-Hakra River of northwestern India has always been considered to be the remnant of an ancient perennial glacier-fed river（Vedic Saraswati）. The exact reason and timing of major hydrological chan...The ephemeral Ghaggar-Hakra River of northwestern India has always been considered to be the remnant of an ancient perennial glacier-fed river（Vedic Saraswati）. The exact reason and timing of major hydrological change of this river remains speculative. The river＇s purported association with the zenith of the Harappan civilisation remains a conjecture because the timings of its fluvial past are still being debated. In this study we have made an attempt to resolve this issue using geochemical provenance of sediments from some dated horizons in the Ghaggar flood plain and that of the material used in the potteries from the Mature Harappan period（4600-3900 yr BP） at Kalibangan. Sampled sedimentary horizons were dated by radiocarbon and optically stimulated luminescence（OSL） methods. Results of our study from the Ghaggar alluvium indicate that the river did have glacial sources during the early Holocene. However, the data from the potteries suggest that during the Mature Harappan period, the sediments in the Ghaggar as used by the potters did not have a higher Himalayan provenance and hence, were not derived from glaciated Himalayas.These findings imply that during the time of the Mature Harappans the Ghaggar had already become a foothill-fed river.展开更多
This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematica...This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematical system to solve the complex computations in an easier manner. There are specific sutras to perform multiplication. Nikhilam sutra is one of the sutra. But this has some limitations. To overcome the limitations, this sutra is combined with Karatsuba algorithm. High speed devices are required for high speed applications with compact size. Normally multipliers require more power for its computation. In this paper, new multiplication algorithm for the multiplication of binary numbers is proposed based on Vedic Mathematics. The novel portion in the algorithm is found to be in the calculation of remainder using complement method. The size of the remainder is always set as N - 1 bit for any combination of input. The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N - 1) bit multiplication. Numerical strength reduction is done through Karatsuba algorithm. The results show that the reduction in hardware leads to reduction in the delay.展开更多
One of the elementary operations in computing systems is multiplication.Therefore,high-speed and low-power multipliers design is mandatory for efficient computing systems.In designing low-energy dissipation circuits,r...One of the elementary operations in computing systems is multiplication.Therefore,high-speed and low-power multipliers design is mandatory for efficient computing systems.In designing low-energy dissipation circuits,reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity.This paper introduces an efficient signed/unsigned 4×4 reversible Vedic multiplier with minimum quantum cost.The Vedic multiplier is considered fast as it generates all partial product and their sum in one step.This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output.First,the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam(UT)Sutra.This multiplier consists of bitwise multiplication and adder compressors.Compared with Vedic multipliers in the literature,the proposed design has a quantum cost of 111 with a reduction of 94%compared to the previous design.It has a garbage output of 30 with optimization of the best-compared design.Second,the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers.Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters.DesignI has separate binary two’s complement(B2C)and MUX circuits,while DesignII combines binary two’s complement and MUX circuits in one circuit.DesignI shows the lowest quantum cost,231,regarding state-ofthe-art.DesignII has a quantum cost of 199,reducing to 86.14%of DesignI.The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.展开更多
文摘In computing architecture, ALU plays a major role. Many promising applications are possible with ATMEGA microcontroller. ALU is a part of these microcontrollers. The performance of these microcontrollers can be improved by applying Reversible Logic and Vedic Mathematics. In this paper, an efficient reversible Arithmetic and Logic Unit with reversible Vedic Multiplier is proposed and the simulation results show its effectiveness in reducing quantum cost, number of gates, and the total number of logical calculations.
文摘In this, today’s world immeasurable analysis goes within the field of communication and signal processing applications. The FIR filter is mostly employed in filtering applications to enhance the quality of the signal. In any processor, the performance of the system is based on the speed of the multiplier unit involved in its operation. Since multiplier forms the indispensable building blocks of the FIR filter system. Its performance has contributed in determining the execution of the FIR filter system. Also, due to the tremendous development in the technology, many approaches such as an array, Vedic methods are made to speed up the multiplier computations. The problem in speed-up operation and resource utilization of hardware with all the conventional methods due to the critical path found in partial products has to be optimized using proposed method. This paper presents the implementation and execution of a FIR Filter design using Anurupye multiplier. Here the FIR filter is examined by using various multiplier algorithms such as Anurupye, Urdhava Tiryagbhyam, and array multipliers. The FIR filter is simulated for analyzing delay;area and power are meted out and lessened by utilizing proposed Anurupye multiplier. The FIR filter design utilizing proposed multiplier offers delay around 18.99 and only 4% of LUT slice utilization compared to existing methods. This architecture is coded in VHDL, simulated using the ModelSim and synthesized with Xilinx.
文摘Decimal multipliers play an important role in our day to day life for commercial, financial and tax applications. Every processor multiplier acts as the basic building block which decides the performance of processor. Time and again research is going on to design high-performance, low-latency BCD multiplier architectures. This paper proposes a new approach to BCD multiplication using vinculum number system. The key feature of the proposed architecture uses entirely a new one digit ROM based BCD multiplier that uses vinculum numbers as operands. Using this one digit BCD multiplier, an N digit BCD multiplier is built by using the vedic vertical cross wire method (Urdhav Triyagbhyam). We have also used our proposed multi operand VBCD Adder (Vinculum BCD Adder) [my paper 26] to add the partial products. In this paper, we show that this approach is a promising alternative to conventional BCD multiplication or other decimal multiplication methods that use alternative decimal representations like 5211, 4221, Xs3 etc.
文摘The Vedic multiplication algorithm is a very fast way of oral calculation. However, the basis of the algorithm is not available so far. The present paper demystifies the general Vedic algorithm for multiplication by establishment of foundation of the Vedic algorithm of product finding through end results of conventional multiplication. This novel approach, i.e., finding algorithm from the end results of conventional calculations may be useful in devising algorithms similar to Vedic in cases of other calculations. Though the availability of cheap calculators made the Vedic Method obsolete, the present trend resurrected Vedic algorithms by their use in the design of computer processors for enhancing speed and performance.
文摘Novel high speed energy efficient square root architecture has been reported in this paper. In this architecture, we have blended ancient Indian Vedic mathematics and Bakhshali mathematics to achieve a significant amount of accuracy in performing the square root operation. Basically, Vedic Duplex method and iterative division method reported in Bakhshali Manuscript have been utilized for that computation. The proposed technique has been compared with the well known Newton-Raphson’s (N-R) technique for square root computation. The algorithm has been implemented and tested using Modelsim simulator, and performance parameters such as the number of lookup tables, propagation delay and power consumption have been estimated using Xilinx ISE simulator. The functionality of the circuitry has been checked using Xilinx Virtex-5 FPGA board.
基金funded by the Department of Space, Government of India
文摘The ephemeral Ghaggar-Hakra River of northwestern India has always been considered to be the remnant of an ancient perennial glacier-fed river（Vedic Saraswati）. The exact reason and timing of major hydrological change of this river remains speculative. The river＇s purported association with the zenith of the Harappan civilisation remains a conjecture because the timings of its fluvial past are still being debated. In this study we have made an attempt to resolve this issue using geochemical provenance of sediments from some dated horizons in the Ghaggar flood plain and that of the material used in the potteries from the Mature Harappan period（4600-3900 yr BP） at Kalibangan. Sampled sedimentary horizons were dated by radiocarbon and optically stimulated luminescence（OSL） methods. Results of our study from the Ghaggar alluvium indicate that the river did have glacial sources during the early Holocene. However, the data from the potteries suggest that during the Mature Harappan period, the sediments in the Ghaggar as used by the potters did not have a higher Himalayan provenance and hence, were not derived from glaciated Himalayas.These findings imply that during the time of the Mature Harappans the Ghaggar had already become a foothill-fed river.
文摘This paper is designed to introduce new hybrid Vedic algorithm to increase the speed of the multiplier. This work combines the principles of Nikhilam sutra and Karatsuba algorithm. Vedic Mathematics is the mathematical system to solve the complex computations in an easier manner. There are specific sutras to perform multiplication. Nikhilam sutra is one of the sutra. But this has some limitations. To overcome the limitations, this sutra is combined with Karatsuba algorithm. High speed devices are required for high speed applications with compact size. Normally multipliers require more power for its computation. In this paper, new multiplication algorithm for the multiplication of binary numbers is proposed based on Vedic Mathematics. The novel portion in the algorithm is found to be in the calculation of remainder using complement method. The size of the remainder is always set as N - 1 bit for any combination of input. The multiplier structure is designed based on Karatsuba algorithm. Therefore, N × N bit multiplication is done by (N - 1) bit multiplication. Numerical strength reduction is done through Karatsuba algorithm. The results show that the reduction in hardware leads to reduction in the delay.
文摘One of the elementary operations in computing systems is multiplication.Therefore,high-speed and low-power multipliers design is mandatory for efficient computing systems.In designing low-energy dissipation circuits,reversible logic is more efficient than irreversible logic circuits but at the cost of higher complexity.This paper introduces an efficient signed/unsigned 4×4 reversible Vedic multiplier with minimum quantum cost.The Vedic multiplier is considered fast as it generates all partial product and their sum in one step.This paper proposes two reversible Vedic multipliers with optimized quantum cost and garbage output.First,the unsigned Vedic multiplier is designed based on the Urdhava Tiryakbhyam(UT)Sutra.This multiplier consists of bitwise multiplication and adder compressors.Compared with Vedic multipliers in the literature,the proposed design has a quantum cost of 111 with a reduction of 94%compared to the previous design.It has a garbage output of 30 with optimization of the best-compared design.Second,the proposed unsigned multiplier is expanded to allow the multiplication of signed numbers as well as unsigned numbers.Two signed Vedic multipliers are presented with the aim of obtaining more optimization in performance parameters.DesignI has separate binary two’s complement(B2C)and MUX circuits,while DesignII combines binary two’s complement and MUX circuits in one circuit.DesignI shows the lowest quantum cost,231,regarding state-ofthe-art.DesignII has a quantum cost of 199,reducing to 86.14%of DesignI.The functionality of the proposed multiplier is simulated and verified using XILINX ISE 14.2.
