摘要
针对现有的单精度浮点乘法器存在运算速度慢的问题,该文设计了一种融合Karatsuba算法和Vedic算法两者优点的快速单精度浮点乘法器。该文利用Karatsuba算法减少单精度浮点乘法器的乘法运算次数,将24 bit尾数的乘法运算分解为少位数乘法运算,获得基于3 bit和4 bit的尾数乘法架构;进一步地,利用Vedic算法对单精度浮点乘法器的尾数乘法架构进行优化,利用复杂度低、速度快的加法器实现了Karatsuba算法分解后的3 bit和4 bit的两个基本乘法运算,提高了运算速度。仿真及FPGA验证结果表明,该文设计的单精度浮点乘法器相对于基于传统的Karatsuba算法的单精度浮点乘法器、基于Vedic算法的单精度浮点乘法器,其最大运行时钟频率分别提高了约5倍和2倍。
To deal with the slow operation speed in the existing single-precision floating-point multiplier,a fast Karatsuba-based single-precision floating-point multiplier which combines the advantages of Karatsuba algorithm with the Vedic algorithm is designed in this paper.The fast Karatsuba-based multiplier decreases the multiplication-operation times of the conventional single-precision floating-point multiplier by splitting the multiplication of 24-bit mantissa into that of fewer mantissa.An improved multiplication architecture composed of the 3-bit and 4-bit mantissa is constructed and further optimized by employing the Vedic algorithm.The 3-bit and 4-bit multipliers are respectively achieved by the corresponding adders with low complexity and fast speed,leading to faster processing speed.The results of simulation and FPGA verification imply that the designed single-precision floating-point multiplier achieves approximately 5 times and 2 times higher performance in the maximum operating clock frequency,comparing to the conventional Karatsuba-based and the Vedic-based single-precision floatingpoint multiplier,respectively.
作者
易清明
符清杆
石敏
骆爱文
陈嘉文
YI Qing-ming;FU Qing-gan;SHI Min;LUO Ai-wen;CHEN Jia-wen(School of Information Science and Technology,Jinan University,Guangzhou,510632;Taidou Microelectronic Science and Technology Co.,Ltd.,Guangzhou,510663)
出处
《电子科技大学学报》
EI
CAS
CSCD
北大核心
2021年第3期368-374,共7页
Journal of University of Electronic Science and Technology of China
基金
中央高校基本科研业务费专项(21620353)
羊城创新创业领军人才支持计划的资助(2019019)。
