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杂质纵向高斯分布UTBB-SOI MOSFET的虚拟阴极阈值电压解析模型
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作者 韦素芬 陈红霞 +2 位作者 李诗勤 黄长斌 刘璟 《集美大学学报(自然科学版)》 CAS 2021年第5期472-480,共9页
采用Sentaurus Process工艺仿真工具,验证了超薄硅膜内单次纵向离子注入并快速热退火后所实现的轻掺杂杂质分布符合高斯规律。设计杂质纵向高斯分布的轻掺杂纳米UTBB-SOI MOSFET,用虚拟阴极处反型载流子浓度来定义阈值电压的方法,为器... 采用Sentaurus Process工艺仿真工具,验证了超薄硅膜内单次纵向离子注入并快速热退火后所实现的轻掺杂杂质分布符合高斯规律。设计杂质纵向高斯分布的轻掺杂纳米UTBB-SOI MOSFET,用虚拟阴极处反型载流子浓度来定义阈值电压的方法,为器件建立二维阈值电压解析模型。通过与Sentaurus Device器件仿真结果对比分析,发现:阈值电压模型能准确预测器件在不同掺杂、器件厚度和偏置电压下的阈值电压,正确反映器件的背栅效应,其模拟结果与理论模型相符。 展开更多
关键词 utbb-soi MOSFET 高斯分布 虚拟阴极 阈值电压
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UTBB SOI MOSFETs短沟道效应抑制技术
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作者 李曼 张淳棠 +3 位作者 刘安琪 姚佳飞 张珺 郭宇锋 《固体电子学研究与进展》 CAS 北大核心 2023年第5期392-400,共9页
随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了... 随着栅极长度、硅膜厚度以及埋氧层厚度的减小,MOS器件短沟道效应变得越来越严峻。本文首先给出了决定全耗尽绝缘体上硅短沟道效应的三种机制;然后从接地层、埋层工程、沟道工程、源漏工程、侧墙工程和栅工程等六种工程技术方面讨论了为抑制短沟道效应而引入的不同UTBB SOI MOSFETs结构,分析了这些结构能够有效抑制短沟道效应(如漏致势垒降低、亚阈值摆幅、关态泄露电流、开态电流等)的机理;而后基于这六种技术,对近年来在UTBB SOI MOSFETs短沟道效应抑制方面所做的工作进行了总结;最后对未来技术的发展进行了展望。 展开更多
关键词 utbb soi MOSFETs 短沟道效应 漏致势垒降低 埋氧层厚度
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28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II
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作者 Ali Mohsen Adnan Harb +1 位作者 Nathalie Deltimple Abraham Serhane 《Circuits and Systems》 2017年第5期111-121,共11页
This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is go... This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor’s architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications. 展开更多
关键词 utbb FD-soi: Ultra-Thin Body and Box Fully Depleted Silicon on Insulator Tri-Gate FINFET DIBL: Drain Induced Barrier Lowering
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28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part I
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作者 Ali Mohsen Adnan Harb +1 位作者 Nathalie Deltimple Abraham Serhane 《Circuits and Systems》 2017年第4期93-110,共18页
Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performanc... Nowadays, transistor technology is going toward the fully depleted architecture;the bulk transistors are becoming more complex in manufacturing as the transistor size is becoming smaller to achieve the high performance especially at the node 28 nm. This is the first of two papers that discuss the basic drawbacks of the bulk transistors and explain the two alternative transistors: 28 nm UTBB FD-SOI CMOS and the 22 nm Tri-Gate FinFET. The accompanying paper, Part II, focuses on the comparison between those alternatives and their physical properties, electrical properties, and reliability tests to properly set the preferences when choosing for different mobile media and consumers’ applications. 展开更多
关键词 utbb FD-soi: Ultra-Thin Body and Box Fully Depleted Silicon on Insulator Tri-Gate FINFET DIBL: Drain Induced Barrier Lowering
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