A track/hold （T/H） circuit of broad bandwidth high speed pipeline structure ADC based on the super frequency application is designed in the paper. Some main factors affecting SNR of high speed ADC, such as aperture ...A track/hold （T/H） circuit of broad bandwidth high speed pipeline structure ADC based on the super frequency application is designed in the paper. Some main factors affecting SNR of high speed ADC, such as aperture uncertainty, switch capacitor, and MOS switch, are analyzed. In the circuit, the full-differential structure and the bottom plate sampling technique are adopted to optimize the switch capacitors and MOS switches. The result based on the Spectre simulation on 0.35pm Bi- CMOS technology indicate that the aperture uncertainty, charge-injection, and non-linearity of clock feed-through are considerably restrained and the performance of T/H circuit is enhanced展开更多
介绍了一个峰保持电路。该电路适用于silicon strip,Si(Li),CdZn Te and CsI等探测器,实现采样-保持功能。已成功进行了基于CMOSFET的采样-保持电路的设计和仿真,通过使用Proteus的PSPICE仿真器和BSIMV3.3模型参数完成了电路性能的仿真...介绍了一个峰保持电路。该电路适用于silicon strip,Si(Li),CdZn Te and CsI等探测器,实现采样-保持功能。已成功进行了基于CMOSFET的采样-保持电路的设计和仿真,通过使用Proteus的PSPICE仿真器和BSIMV3.3模型参数完成了电路性能的仿真。同时,实现了采样时间可在60ns到4.44s范围内进行选择,该电路具有较好的线性。展开更多
针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器...针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器。采用55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明,该ADC实现了34 dB SNDR、36 dB SFDR和1.6 GHz的模拟输入信号带宽。该ADC的版图面积为670μm×390μm,功耗为9.6 mW。展开更多
A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-samplin...A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm^2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.展开更多
Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calcula...Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method. The other calculates the weekly nonlinear distortion by using a Volterra series method and a nodal formulation. Comparative calculation results for the diode bridge THA have shown good agreement with these two computer program calculation methods, whereas the overall computational efficiency of the nonlinear-current method is better than that of the nodal formulation method in a special evaluation.展开更多
In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, highspeed flash analogtodigital converters （ADCs）. In [1], we theoretically describ the calibration techniqu...In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, highspeed flash analogtodigital converters （ADCs）. In [1], we theoretically describ the calibration technique and perform a behaviorallevel simulation to test its functionality [1]. In this work, we discuss some issues in transistorlevel implementation. The predominant factors that contribute to static errors such as reference generator mismatch and trackandhold （T/H） gain error can be treated as inputreferred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistorlevel implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.展开更多
Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrappe...Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrapped and bulk-switching technique is introduced to greatly minimize the nonlinearity of sampling network over a wide bandwidth, and the addition of a modified pre-charge circuit helps reducing the total power consumption. The experimental results show that the proposed T/H circuit achieves over 77 dB SFDR （spurious-free dynamic range） and 70 dB THD （total harmonic distortion） at 100 MHz sampling rate and maintains the performance with input frequency up to 305 MHz while consuming 47 mW power.展开更多
An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to a...An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18/zm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mme. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is -48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.展开更多
文摘A track/hold （T/H） circuit of broad bandwidth high speed pipeline structure ADC based on the super frequency application is designed in the paper. Some main factors affecting SNR of high speed ADC, such as aperture uncertainty, switch capacitor, and MOS switch, are analyzed. In the circuit, the full-differential structure and the bottom plate sampling technique are adopted to optimize the switch capacitors and MOS switches. The result based on the Spectre simulation on 0.35pm Bi- CMOS technology indicate that the aperture uncertainty, charge-injection, and non-linearity of clock feed-through are considerably restrained and the performance of T/H circuit is enhanced
基金National Natural Science Foundation of China(10735060)Fund of Third World Academy of Sciences~~
文摘介绍了一个峰保持电路。该电路适用于silicon strip,Si(Li),CdZn Te and CsI等探测器,实现采样-保持功能。已成功进行了基于CMOSFET的采样-保持电路的设计和仿真,通过使用Proteus的PSPICE仿真器和BSIMV3.3模型参数完成了电路性能的仿真。同时,实现了采样时间可在60ns到4.44s范围内进行选择,该电路具有较好的线性。
文摘针对软件无线电架构的导航接收机对模数转换器的高输入带宽、高速及低功耗的需求,通过集成低功耗宽带采样保持电路及新型非二进制权重的电容阵列数模转换器电路,采用逐次逼近型模数转换器架构,设计实现了一款射频直接采样SAR模数转换器。采用55 nm CMOS工艺电路设计、版图设计、仿真及硅流片验证,测试结果表明,该ADC实现了34 dB SNDR、36 dB SFDR和1.6 GHz的模拟输入信号带宽。该ADC的版图面积为670μm×390μm,功耗为9.6 mW。
基金Project supported by the National High Technology Research and Development Program of China(No.2009AA01Z261)the State Key Laboratory of Wireless Telecommunication,Southeast University
文摘A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier（THA） in 0.13μm CMOS for an impulse radio ultra-wideband（IR-UWB） receiver is presented.The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency.This paper presents,to our knowledge for the second time,a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz.In this design,a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz.A resistive averaging technique is carefully analyzed to relieve noise aliasing.A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed,power consumption and noise aliasing.The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s.The core power of the ADC is 30 mW,excluding all of the buffers,and the active area is 0.6 mm^2.The ADC achieves a figure of merit of 3.75 pJ/conversion-step.
文摘Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method. The other calculates the weekly nonlinear distortion by using a Volterra series method and a nodal formulation. Comparative calculation results for the diode bridge THA have shown good agreement with these two computer program calculation methods, whereas the overall computational efficiency of the nonlinear-current method is better than that of the nodal formulation method in a special evaluation.
文摘In this paper, we focus on practical issues in implementing a calibration technique for medium-resolution, highspeed flash analogtodigital converters （ADCs）. In [1], we theoretically describ the calibration technique and perform a behaviorallevel simulation to test its functionality [1]. In this work, we discuss some issues in transistorlevel implementation. The predominant factors that contribute to static errors such as reference generator mismatch and trackandhold （T/H） gain error can be treated as inputreferred offsets of each comparator. Using the proposed calibration technique, these errors can be calibrated with minimal detriment to the dynamic performance of the converter. We simulate a transistorlevel implementation of a 5-bit, 1 GHz ADC in a 1.2 V, 65 nm CMOS process. The results show that DNL can be improved from 2.5 LSB to below 0.7 LSB after calibration, and INL can be improved from 1.6 LSB to below 0.6 LSB after calibration.
文摘Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrapped and bulk-switching technique is introduced to greatly minimize the nonlinearity of sampling network over a wide bandwidth, and the addition of a modified pre-charge circuit helps reducing the total power consumption. The experimental results show that the proposed T/H circuit achieves over 77 dB SFDR （spurious-free dynamic range） and 70 dB THD （total harmonic distortion） at 100 MHz sampling rate and maintains the performance with input frequency up to 305 MHz while consuming 47 mW power.
基金supported by the PhD Programs Foundation of Ministry of Education of China(No.2009009211001)the Important National Science&Technology Specific Projects(No.2010ZX03006-003-02)
文摘An open-loop 20 GSps track-and-hold amplifier （THA） using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18/zm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mme. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is -48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.
