摘要
Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrapped and bulk-switching technique is introduced to greatly minimize the nonlinearity of sampling network over a wide bandwidth, and the addition of a modified pre-charge circuit helps reducing the total power consumption. The experimental results show that the proposed T/H circuit achieves over 77 dB SFDR （spurious-free dynamic range） and 70 dB THD （total harmonic distortion） at 100 MHz sampling rate and maintains the performance with input frequency up to 305 MHz while consuming 47 mW power.
Design of a high performance track and hold （T/H） circuit for high-resolution high-speed analog-to-digital converter （ADC） is presented, which has been implemented in 0.18 μm CMOS process. An improved bootstrapped and bulk-switching technique is introduced to greatly minimize the nonlinearity of sampling network over a wide bandwidth, and the addition of a modified pre-charge circuit helps reducing the total power consumption. The experimental results show that the proposed T/H circuit achieves over 77 dB SFDR （spurious-free dynamic range） and 70 dB THD （total harmonic distortion） at 100 MHz sampling rate and maintains the performance with input frequency up to 305 MHz while consuming 47 mW power.
