时间交织采样是提高模数转换器采样率的一种有效途径。为了完成时间交织采样的通道失配误差方法评估,提出并设计了一套基于4通道时间交织的FPGA高速模数转换采样系统。系统由前端模拟电路、采样阵列、多相时钟电路模块、基于FPGA的数据...时间交织采样是提高模数转换器采样率的一种有效途径。为了完成时间交织采样的通道失配误差方法评估,提出并设计了一套基于4通道时间交织的FPGA高速模数转换采样系统。系统由前端模拟电路、采样阵列、多相时钟电路模块、基于FPGA的数据缓冲与修正处理模块构成。系统采样输出数据通过上传到上位机进行显示与性能指标分析。测试结果表明,该TIADC系统通过对失配误差的数字后端补偿后能稳定工作在1 GS/s采样率。其采样有效位与平均信噪比分别达到7.03 bit与44.1 d B,可以应用于采样失配修正方法的验证与评估。展开更多
A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels ...A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.展开更多
Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch erro...Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limi- tation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit l-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.展开更多
为了解决海量数据的高速传输问题,本文以AXIe(Advanced TCA Extensions for Instrumentation)总线为传输架构,重点设计数据的高速缓存和传输接口,并设计时间交织数据采集模块完成AXIe数据采集传输接口验证.通过两片ADC实现时间交织数据...为了解决海量数据的高速传输问题,本文以AXIe(Advanced TCA Extensions for Instrumentation)总线为传输架构,重点设计数据的高速缓存和传输接口,并设计时间交织数据采集模块完成AXIe数据采集传输接口验证.通过两片ADC实现时间交织数据采样功能,将DDR3作为数据的深存储单元,采用PCI Express实现数据高速传输.在FPGA上完成设计,使用ILA嵌入式逻辑分析仪进行功能验证.结果表明,该设计能很好地实现交织采样功能,完成基于AXIe总线的数据传输.展开更多
High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an ef...High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an effective candidate to implement wide-band ADC with relatively slow circuits accounting for digital spectrum management. However, practical performance of TI-ADC is largely limited because of mismatches between different channels originated from manufacturing process variations. In this paper, a blind adaptive method is proposed to correct gain mismatch errors in TI-ADC, and it is verified through simulations on a two-channel TI-ADC. In proposed method, gain mismatch error is estimated and corrected in an adaptive scheme. Proposed compensated T1-ADC architecture is structurally very simple and hence suitable for realiza- tion in integrated circuits. Besides, proposed digital compensation algorithm not only is computationally efficient but also provides an improvement of 32.7 dB in the performance of two-channel TI ADC.展开更多
Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is pro...Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.展开更多
This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the...This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.展开更多
A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by non...A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero（TRI-DRRZ）.Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.展开更多
文摘时间交织采样是提高模数转换器采样率的一种有效途径。为了完成时间交织采样的通道失配误差方法评估,提出并设计了一套基于4通道时间交织的FPGA高速模数转换采样系统。系统由前端模拟电路、采样阵列、多相时钟电路模块、基于FPGA的数据缓冲与修正处理模块构成。系统采样输出数据通过上传到上位机进行显示与性能指标分析。测试结果表明,该TIADC系统通过对失配误差的数字后端补偿后能稳定工作在1 GS/s采样率。其采样有效位与平均信噪比分别达到7.03 bit与44.1 d B,可以应用于采样失配修正方法的验证与评估。
基金Supported by the National Natural Science Foundation of China (No. 61076026)
文摘A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.
基金Supported by Knowledge Innovation Program of Chinese Academy of Sciences(KJCX2-YW-N27)National Natural Science Foundation of China(11175176,10476028)
文摘Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limi- tation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit l-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.
基金Iran’s Telecommunication Research Center(ITRC)(No.500/3653)
文摘High spectral efficiency is essential in design of multimedia communication systems such as L-band mobile in addition to various requirements of transmission quality. Time-interleaved A/D converter （TI-ADC） is an effective candidate to implement wide-band ADC with relatively slow circuits accounting for digital spectrum management. However, practical performance of TI-ADC is largely limited because of mismatches between different channels originated from manufacturing process variations. In this paper, a blind adaptive method is proposed to correct gain mismatch errors in TI-ADC, and it is verified through simulations on a two-channel TI-ADC. In proposed method, gain mismatch error is estimated and corrected in an adaptive scheme. Proposed compensated T1-ADC architecture is structurally very simple and hence suitable for realiza- tion in integrated circuits. Besides, proposed digital compensation algorithm not only is computationally efficient but also provides an improvement of 32.7 dB in the performance of two-channel TI ADC.
基金supported by the National Natural Science Foundation of China(No.61006025)the Special Research Funds for Doctoral Program of Higher Education of China(No.20100071110026)
文摘Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters （TIADCs）.A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper.The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals.The detected sample-time error is corrected by a voltage-controlled sampling switch.The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB,and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration.The calibration convergence time is about 20000 sampling intervals.
文摘This paper proposes a digital background calibration scheme for timing skew in time-interleaved analog-to-digital converters (TIADCs). It detects the relevant timing error by subtracting the output difference with the sum of the first derivative of the digital output. The least-mean-square (LMS) loop is exploited to compensate the timing skew. Since the calibration scheme depends on the digital output, all timing skew sources can be calibrated and the main ADC is maintained. The proposed scheme is effective within the entire frequency range of 0 ? fs/2. Compared with traditional calibration schemes, the proposed approach is more feasible and consumes significantly lesser power and smaller area.
基金supported by the National High Technology Research and Development Program of China(No.SS2013AA011203)the Specialized Research Fund for the Doctoral Program of Higher Education of China(No.20110002110058)
文摘A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero（TRI-DRRZ）.Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.
