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Design and Fabrication of Thermo-Optic 4×4 Switching Matrix in Silicon-on-Insulator 被引量:5
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作者 王章涛 樊中朝 +2 位作者 夏金松 陈少武 余金中 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2004年第12期1573-1575,共3页
A rearrangeable nonblocking thermo-optic 4×4 switching matrix,which consists of five 2×2 multimode interference-based Mach-Zehnder interferometer(MMI-MZI) switch elements,is designed and fabricated.The minim... A rearrangeable nonblocking thermo-optic 4×4 switching matrix,which consists of five 2×2 multimode interference-based Mach-Zehnder interferometer(MMI-MZI) switch elements,is designed and fabricated.The minimum and maximum excess loss for the matrix are 6.6 and 10.4dB,respectively.The crosstalk in the matrix is measured to be between -12 and -19.8dB.The switching speed of the matrix is less than 30μs.The power consumption for the single switch element is about 330mW. 展开更多
关键词 integrated optics silicon-ON-insulator matrix switches PLC technology
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A 10-MHz SOI-Based Face Shear Square Micromechanical Resonator
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作者 Tan-Loc Nguyen Jing-Fu Bao +2 位作者 Jun-Wen Jiang Yuan Ling Xin-Yi Li 《Journal of Electronic Science and Technology》 CAS 2014年第1期64-70,共7页
A 10-MHz face shear (FS) square micro- mechanical resonator based on silicon-on-insulator (SO1) technology is presented in this paper. In order to examine the improvement of quality factor as well as motional resi... A 10-MHz face shear (FS) square micro- mechanical resonator based on silicon-on-insulator (SO1) technology is presented in this paper. In order to examine the improvement of quality factor as well as motional resistance Rx in this structure, the center-stem anchor is employed in this study. The benefit of anchoring the square in the center, which is the nodal point, is that the energy losses through the anchor can be minimized. Hence, a quality factor value of 2.0 million and the motional resistance of 8.2 k~ can be obtained with an FS mode resonator via finite element (FE) simulation. The results show the significance of the FS mode in this design, not only in its structure but also in its square-extensional mode and Lame-mode. Additionally, an SOI-based fabrication process is proposed to support the design. 展开更多
关键词 Face shear mode finite elementsimulation micromechanicai resonator quality factor silicon-on-insulator technology.
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Total Ionizing Dose Response of Different Length Devices in 0.13μm Partially Depleted Silicon-on-Insulator Technology 被引量:1
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作者 张梦映 胡志远 +4 位作者 张正选 樊双 戴丽华 刘小年 宋雷 《Chinese Physics Letters》 SCIE CAS CSCD 2017年第8期144-147,共4页
An anomalous total dose effect that the long length device is more susceptible to total ionizing dose than the short one is observed with the 0.13?μm partially depleted silicon-on-insulator technology. The measured ... An anomalous total dose effect that the long length device is more susceptible to total ionizing dose than the short one is observed with the 0.13?μm partially depleted silicon-on-insulator technology. The measured results and 3D technology computer aided design simulations demonstrate that the devices with different channel lengths may exhibit an enhanced reverse short channel effect after radiation. It is ascribed to that the halo or pocket implants introduced in processes results in non-uniform channel doping profiles along the device length and trapped charges in the shallow trench isolation regions. 展开更多
关键词 PDSOI Total Ionizing Dose Response of Different Length Devices in 0.13 m Partially Depleted silicon-on-insulator technology
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SOI技术及其设备
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作者 翁寿松 《电子工业专用设备》 2006年第3期43-45,共3页
介绍了SOI技术的特点和制造方法、超薄SOI技术,应变硅SOI技术及其设备,如大束流专用氧离子注入机。
关键词 SOI技术 超薄SOI 应变硅SOI 大柬流 专用氧离子注入机
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Photonic integrated circuit components based on amorphous silicon-on-insulator technology
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作者 Timo Lipka Lennart Moldenhauer +1 位作者 Jorg Muller Hoc Khiem Trieu 《Photonics Research》 SCIE EI 2016年第3期126-134,共9页
We present integrated-optic building blocks and functional photonic devices based on amorphous siliconon-insulator technology. Efficient deep-etched fiber-to-chip grating couplers, low-loss single-mode photonic wire w... We present integrated-optic building blocks and functional photonic devices based on amorphous siliconon-insulator technology. Efficient deep-etched fiber-to-chip grating couplers, low-loss single-mode photonic wire waveguides, and compact power splitters are presented. Based on the sub-μm photonic wires, 2 × 2 Mach–Zehnder interferometers and add/drop microring resonators(MRRs) with low device footprints and high finesse up to 200 were realized and studied. Compact polarization rotators and splitters with ≥10 d B polarization extinction ratio were fabricated for the polarization management on-chip. The tuning and trimming capabilities of the material platform are demonstrated with efficient microheaters and a permanent device trimming method, which enabled the realization of energy-efficient photonic circuits. Wavelength multiplexers in the form of cascaded filter banks and 4 × 4 routers based on MRR switches are presented. Fabrication imperfections were analyzed and permanently corrected by an accurate laser-trimming method, thus enabling eight-channel multiplexers with record low metrics of sub-m W static power consumption and ≤1°C temperature overhead. The high quality of the functional devices, the high tuning efficiency, and the excellent trimming capabilities demonstrate the potential to realize low-cost, densely integrated, and ultralow-power 3D-stacked photonic circuits on top of CMOS microelectronics. 展开更多
关键词 Photonic integrated circuit components based on amorphous silicon-on-insulator technology SOI MRR OADM
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0.18 μm SOI工艺抗辐照触发器性能研究 被引量:1
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作者 周昕杰 于宗光 +1 位作者 田海燕 陈嘉鹏 《固体电子学研究与进展》 CAS CSCD 北大核心 2014年第5期460-464,共5页
随着集成电路制造工艺尺寸不断减小、集成度不断提高,集成电路在太空环境应用中更容易受到单粒子辐照效应的影响,可靠性问题越发严重。特别是对高频数字电路而言,单粒子翻转效应(SEU)及单粒子瞬态扰动(SET)会导致数据软错误。虽然以往... 随着集成电路制造工艺尺寸不断减小、集成度不断提高,集成电路在太空环境应用中更容易受到单粒子辐照效应的影响,可靠性问题越发严重。特别是对高频数字电路而言,单粒子翻转效应(SEU)及单粒子瞬态扰动(SET)会导致数据软错误。虽然以往的大尺寸SOI工艺,具有很好的抗单粒子性能,但仍需要对深亚微米SOI电路进行辐照效应研究。文中通过对4种触发器链进行抗辐照设计,用0.18μm SOI工艺进行了流片验证,并与体硅CMOS工艺对比分析。1.8V电源电压条件下的触发器翻转阈值可以达到41.7MeV·cm2/mg,抗辐射性能比0.18μm体硅CMOS工艺提升了约200%。 展开更多
关键词 辐照效应 辐射加固 触发器 绝缘体上硅工艺
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全耗尽绝缘体上硅氧化铪基铁电场效应晶体管存储单元单粒子效应计算机模拟研究
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作者 沈睿祥 张鸿 +6 位作者 宋宏甲 侯鹏飞 李波 廖敏 郭红霞 王金斌 钟向丽 《物理学报》 SCIE EI CAS CSCD 北大核心 2022年第6期363-370,共8页
铁电场效应晶体管具有非挥发性、低功耗、读写速度快等优异的存储性能,是最有前景的新型半导体存储器件之一.为促进铁电场效应晶体管在辐射环境中的应用,本文利用计算机辅助设计软件对全耗尽绝缘体上硅氧化铪基铁电场效应晶体管存储单... 铁电场效应晶体管具有非挥发性、低功耗、读写速度快等优异的存储性能,是最有前景的新型半导体存储器件之一.为促进铁电场效应晶体管在辐射环境中的应用,本文利用计算机辅助设计软件对全耗尽绝缘体上硅氧化铪基铁电场效应晶体管存储单元的单粒子效应进行研究,分析了重离子不同入射位置及角度和漏极偏置电压对存储单元相关特性的影响.结果表明:重离子入射位置改变不会使氧化铪铁电层中相应的极化状态发生反向,但会影响存储单元输出电压瞬态变化,最敏感区域靠近漏-体结区域;随着重离子入射角度减小,存储单元输出电压峰值增大,读数据“0”时入射角度变化的影响更为明显;存储单元输出电压峰值受漏极偏置电压调制,读数据“1”时调制效应更为明显.本工作为全耗尽绝缘体上硅氧化铪基铁电场效应晶体管存储单元抗单粒子效应加固设计提供理论依据和指导. 展开更多
关键词 全耗尽绝缘体上硅 铁电场效应晶体管 单粒子效应 计算机辅助设计
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基于硅隔离技术的耐高温压力传感器研究 被引量:8
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作者 赵玉龙 赵立波 蒋庄德 《西安交通大学学报》 EI CAS CSCD 北大核心 2002年第11期1156-1158,共3页
采用硅隔离SoI(SilicononInsulator)技术 ,应用高能氧离子的注入方法 ,在单晶硅材料中形成埋层二氧化硅 ,用以隔离作为测量电路的顶部硅层与体硅之间因温度升高而造成的漏电流 .采用梁膜结合的压力传递机构 ,将被测压力与SoI敏感元件隔... 采用硅隔离SoI(SilicononInsulator)技术 ,应用高能氧离子的注入方法 ,在单晶硅材料中形成埋层二氧化硅 ,用以隔离作为测量电路的顶部硅层与体硅之间因温度升高而造成的漏电流 .采用梁膜结合的压力传递机构 ,将被测压力与SoI敏感元件隔离开来 ,因此避免了被测压力的瞬时高温冲击 .给出了传感器的结构模型和实验数据 ,测试结果表明 ,这种新型结构的耐高压力传感器 ,具有较好的动静态特性 . 展开更多
关键词 硅隔离技术 耐高温压力传感器 压力传递机构 离子注入 敏感元件 压力测量
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一种新的SOI制备技术:H^+离子注入、键合和分离 被引量:6
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作者 竺士场 张苗 +3 位作者 林成鲁 黄宜平 吴东平 李金华 《Journal of Semiconductors》 EI CAS CSCD 北大核心 1997年第9期706-709,共4页
H+离子注入Si片并经一定条件退火,可在Si片中形成埋层微空腔(microcavity)层,结合Si片键合技术,用智能剥离(Smart-cut)技术成功地制备了Unibond-SOI材料,并用扩展电阻(SRP)、卢瑟福背散射(RBS/C)和剖面透射电子显微镜(... H+离子注入Si片并经一定条件退火,可在Si片中形成埋层微空腔(microcavity)层,结合Si片键合技术,用智能剥离(Smart-cut)技术成功地制备了Unibond-SOI材料,并用扩展电阻(SRP)、卢瑟福背散射(RBS/C)和剖面透射电子显微镜(XTEM)等初步分析了其结构和电学性质. 展开更多
关键词 SOI制备技术 硅片 离子注入 键合 分离
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深亚微米薄层SOI/MOSFET’s热载流子效应分析 被引量:3
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作者 曹建民 吴传良 +1 位作者 沈文正 黄敞 《Journal of Semiconductors》 EI CAS CSCD 北大核心 1998年第4期280-286,共7页
本文从二维模拟热载流子注入电流入手,讨论了不同硅层厚度、栅氧厚度和掺杂浓度对薄层深亚微米SOI/MOSFET’s热载流子效应的影响.模拟结果表明,对于不同的硅层厚度,沟道前表面漏结处的载流子浓度对热载流子效应起着不同... 本文从二维模拟热载流子注入电流入手,讨论了不同硅层厚度、栅氧厚度和掺杂浓度对薄层深亚微米SOI/MOSFET’s热载流子效应的影响.模拟结果表明,对于不同的硅层厚度,沟道前表面漏结处的载流子浓度对热载流子效应起着不同的作用,有时甚至是决定性的作用.沟道前表面漏结处的载流子浓度和沟道最大电场一样,是影响薄层SOI/MOSFET’s热载流子效应的重要因素,这也就解释了以往文献中,随着硅层减薄,沟道电场增大,热载流子效应反而减小的矛盾.模拟也显示了在一定的硅层厚度变化范围内(60~100nm),器件热载流子效应达到最小值,而且在这一硅层范围内,热载流子效应对硅层厚度、栅氧厚度以及掺杂浓度的变化不敏感,这对高性能深亚微米薄层SOI/MOSFET’s设计具有重要的指导意义. 展开更多
关键词 SOI/MOSFET VLSI 半导体器件 热载子效应
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采用混合模式晶体管(BMHMT)构成低温BiCMOS集成电路 被引量:3
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作者 李树荣 郭维廉 +2 位作者 郑云光 刘理天 李志坚 《Journal of Semiconductors》 EI CAS CSCD 北大核心 1998年第9期715-720,共6页
本文介绍采用与CMOS工艺完全相容的双极/MOS混合模式晶体管(BMHMT)构成新型的低温BiCMOS集成电路.理论分析表明该电路与CMOS相比,在电压摆幅相同,静态功耗相近的条件下,具有更大的驱动能力,尤其在较低的... 本文介绍采用与CMOS工艺完全相容的双极/MOS混合模式晶体管(BMHMT)构成新型的低温BiCMOS集成电路.理论分析表明该电路与CMOS相比,在电压摆幅相同,静态功耗相近的条件下,具有更大的驱动能力,尤其在较低的工作电压下,其特点更加突出.我们用统一的标准和相同芯片面积设计了39级带负载的BiCMOS和CMOS环形振荡器.实验样品经室温和低温平均门延迟时间测试,表明在相同工作电压下BiCMOS优于CMOS.若两种电路都采用SOI结构。 展开更多
关键词 混合模式晶体管 VLSI BMHMT IC 铋CMOS 制造工艺
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在SOI材料上制备高质量的氧化铪薄膜 被引量:3
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作者 邢玉梅 陶凯 +4 位作者 俞跃辉 郑志宏 杨文伟 宋朝瑞 沈达身 《功能材料》 EI CAS CSCD 北大核心 2004年第6期736-738,共3页
 用电子束蒸发氧化铪靶的方法,在SOI(绝缘体上硅)材料上制备了氧化铪薄膜,随后在氮气中进行快速退火(600℃,300s)。借助掠角X射线衍射(GAXRD)、X射线光电子能谱(XPS)、高分辨透射电镜(HRTEM)技术分析了样品的微观结构,研究了样品在退...  用电子束蒸发氧化铪靶的方法,在SOI(绝缘体上硅)材料上制备了氧化铪薄膜,随后在氮气中进行快速退火(600℃,300s)。借助掠角X射线衍射(GAXRD)、X射线光电子能谱(XPS)、高分辨透射电镜(HRTEM)技术分析了样品的微观结构,研究了样品在退火前后发生的组成及结构变化,结果表明退火后氧化铪薄膜由退火前的非晶态转变为单斜结构的多晶态,薄膜中的O/Hf原子比较退火前更接近化学计量比2。借助扩展电阻探针(SRP)技术考察了退火前后薄膜的电学性能,证明在SOI材料上制备的多晶氧化铪薄膜同样具有较好的电介质绝缘性能。 展开更多
关键词 SOI材料 氧化铪 薄膜
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Performance testing of log pile photonic crystal fast-fabricated by direct femtosecond laser writing 被引量:2
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作者 杨海峰 周明 +2 位作者 戴娟 狄建科 赵恩兰 《Chinese Optics Letters》 SCIE EI CAS CSCD 2008年第11期864-867,共4页
Great efforts has been made on fabricating photonic crystals (PCs) with photonic band gaps (PBGs) during the past decade. Three-dimensional (3D) log pile PC was fabricated fast by direct femtosecond laser writin... Great efforts has been made on fabricating photonic crystals (PCs) with photonic band gaps (PBGs) during the past decade. Three-dimensional (3D) log pile PC was fabricated fast by direct femtosecond laser writing in ORMOCER. Qualitative analysis of the errors of PC was investigated using the Image Pro Plus. Surface qualities such as bending, distortion, and surface roughness were shown, and the band gap in the infrared wavelength region was observed. Meanwhile, the theory was experimentally verified that the center of PBG diminishes as the crystal lattice period reduces. Therefore, it is possible to fabricate PCs whose band gap range is from the near-infrared to visible wave band. 展开更多
关键词 Crystal atomic structure CRYSTALLOGRAPHY Energy gap Gallium alloys Microcomputers Photonic band gap PHOTONICS PILES Pulsed laser applications silicon on insulator technology Surface roughness Three dimensional Ultrashort pulses
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High-speed electrooptical VOA integrated in silicon-on-insulator 被引量:1
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作者 严清峰 余金中 +1 位作者 夏金松 刘忠立 《Chinese Optics Letters》 SCIE EI CAS CSCD 2003年第4期217-219,共3页
In this paper, we present simulation results of an electrooptical variable optical attenuator (VOA) integrated in silicon-on-insulator waveguide. The device is functionally based on free carriers absorption to achieve... In this paper, we present simulation results of an electrooptical variable optical attenuator (VOA) integrated in silicon-on-insulator waveguide. The device is functionally based on free carriers absorption to achieve attenuation. Beam propagation method (BPM) and two-dimensional semiconductor device simulation tool PISCES-II were used to analyze the dc and transient characteristics of the device. The device has a response time (including rise time and fall time) less than 200 ns, much faster than the thermooptic and micro-electromechanical systems (MEMSs) based VOAs. 展开更多
关键词 ATTENUATION Electrooptical effects silicon on insulator technology Waveguide attenuators
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SOI thermo-optic modulator with fast response 被引量:1
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作者 王小龙 刘敬伟 +2 位作者 严清峰 陈绍武 余金中 《Chinese Optics Letters》 SCIE EI CAS CSCD 2003年第9期527-528,共2页
Silicon-on-insulator (SOI) technology offers tremendous potential for integration of optoelectronic functions on a silicon wafer. In this letter, a 1 x 1 multimode interference (MMI) Mach-Zender interferometer (MZI) t... Silicon-on-insulator (SOI) technology offers tremendous potential for integration of optoelectronic functions on a silicon wafer. In this letter, a 1 x 1 multimode interference (MMI) Mach-Zender interferometer (MZI) thermo-optic modulator fabricated by wet-etching method is demonstrated. The modulator has an extinction ratio of -11.0 dB, extra loss of -4.9 dB and power consumption of 420 mW. The response time is less than 30 us. 展开更多
关键词 INTERFEROMETERS Optoelectronic devices silicon on insulator technology
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Three-step lithography to the fabrication of vertically coupled micro-ring resonators in amorphous silicon-on-insulator 被引量:2
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作者 程俊 严楠 《Chinese Optics Letters》 SCIE EI CAS CSCD 2015年第8期100-104,共5页
A simple method to fabricate vertically coupled micro-ring resonators in amorphous silicon-on-insulator is created by a three-step lithography process. First, the linear loss at 1.55 μm of the a-Si:H film is calcula... A simple method to fabricate vertically coupled micro-ring resonators in amorphous silicon-on-insulator is created by a three-step lithography process. First, the linear loss at 1.55 μm of the a-Si:H film is calculated to be 0.2 =k 0.05 dB/cm. Then, the bottom line waveguide of Su-8 with a flat top surface of 300 nm is created by etching. The thickness of Su-8 can easily be controlled by the etching time. Finally, by opening the window pattern and etching several layers, the first layer marks made by electron beam lithography are found with a 50 nm resolution, and the high quality of the micro-ring resonator is demonstrated. 展开更多
关键词 Electron beam lithography ETCHING LITHOGRAPHY Optical resonators Resonators silicon on insulator technology
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Reverse current reduction of Ge photodiodes on Si without post-growth annealing 被引量:1
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作者 Sungbong Park Shinya Takita +2 位作者 Yasuhiko Ishikawa Jiro Osaka Kazumi Wada 《Chinese Optics Letters》 SCIE EI CAS CSCD 2009年第4期286-290,共5页
A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth... A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth annealing, the reverse current density is reduced to -10 mA/cm^2 at -1 V, i.e., over one order of magnitude lower than that of the reference photodiode without i-Si layer. However, the responsivity of the photodiodes is not severely compromised. This lowered-reverse-current is explained by band-pinning at the i-Si/i-Ge interface. Barrier lowering mechanism induced by E-field is also discussed. The presented "non-thermal" approach to reduce reverse current should accelerate electronics-photonics convergence by using Oe on the Si complementary metal oxide semiconductor (CMOS) platform. 展开更多
关键词 CMOS integrated circuits Electric fields GERMANIUM METALS MOS devices Oxide semiconductors Photodiodes silicon silicon on insulator technology
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高温SOI技术的发展现状和前景 被引量:3
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作者 罗宁胜 曹建武 《电子与封装》 2022年第12期85-93,共9页
高温绝缘层上硅(SOI)技术突破了体硅半导体器件的高温困境,已被广泛应用于石油天然气钻探、航空航天和国防装备等尖端领域。近年来,第三代宽禁带半导体功率器件已日趋成熟和普及,其中SiC器件以其先天的耐高压、耐高温等特性,与高温SOI... 高温绝缘层上硅(SOI)技术突破了体硅半导体器件的高温困境,已被广泛应用于石油天然气钻探、航空航天和国防装备等尖端领域。近年来,第三代宽禁带半导体功率器件已日趋成熟和普及,其中SiC器件以其先天的耐高压、耐高温等特性,与高温SOI器件是非常理想的搭配,适用于原本体硅半导体功率器件难以实现或根本不能想象的应用场景,为系统应用设计者提供了全新的拓展空间。在简述体硅半导体器件高温困境的基础上,综述了高温SOI技术的发展现况,并探讨了其未来的发展方向和应用前景。 展开更多
关键词 体硅 绝缘层上硅 SIC 高温SOI技术
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基于TCAD的绝缘体上硅器件总剂量效应仿真技术研究 被引量:3
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作者 彭超 雷志锋 +3 位作者 张战刚 何玉娟 黄云 恩云飞 《电子学报》 EI CAS CSCD 北大核心 2019年第8期1755-1761,共7页
绝缘体上硅(Silicon-on-Insulator,SOI)器件的全介质隔离结构改善了其抗单粒子效应性能,但也使其对总剂量效应更加敏感.为了评估SOI器件的总剂量效应敏感性,本文提出了一种基于TCAD(Technology Computer Aided Design)的总剂量效应仿真... 绝缘体上硅(Silicon-on-Insulator,SOI)器件的全介质隔离结构改善了其抗单粒子效应性能,但也使其对总剂量效应更加敏感.为了评估SOI器件的总剂量效应敏感性,本文提出了一种基于TCAD(Technology Computer Aided Design)的总剂量效应仿真技术.通过对SOI器件三维结构进行建模,利用TCAD内置的辐射模型开展瞬态仿真,模拟氧化层中辐射感应电荷的产生、输运和俘获过程,从而分别评估绝缘埋层(Buried Oxide,BOX)和浅沟槽隔离(Shallow Trench Isolation,STI)氧化层中辐射感应陷阱电荷对器件电学性能的影响.基于该仿真技术,本文分别研究了不同偏置、沟道长度、体区掺杂浓度以及STI形貌对SOI MOSFET器件总剂量辐射效应的影响.仿真结果表明高浓度的体区掺杂、较小的STI凹槽深度和更陡峭的STI侧壁将有助于改善SOI器件的抗总剂量效应性能. 展开更多
关键词 绝缘体上硅 总剂量效应 浅沟槽隔离 TCAD仿真
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基于130nm SOI工艺数字ASIC ESD防护设计 被引量:3
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作者 米丹 周昕杰 周晓彬 《半导体技术》 CAS 北大核心 2021年第4期279-285,共7页
绝缘体上硅(SOI)工艺具有寄生电容小、速度快和抗闩锁等优点,成为低功耗和高性能集成电路(IC)的首选。但SOI工艺IC更易受自加热效应(SHE)的影响,因此静电放电(ESD)防护设计成为一大技术难点。设计了一款基于130 nm部分耗尽型SOI(PD-SOI... 绝缘体上硅(SOI)工艺具有寄生电容小、速度快和抗闩锁等优点,成为低功耗和高性能集成电路(IC)的首选。但SOI工艺IC更易受自加热效应(SHE)的影响,因此静电放电(ESD)防护设计成为一大技术难点。设计了一款基于130 nm部分耗尽型SOI(PD-SOI)工艺的数字专用IC(ASIC)。针对SOI工艺ESD防护设计难点,进行了全芯片ESD防护原理分析,通过对ESD防护器件、I/O管脚ESD防护电路、电源钳位电路和ESD防护网络的优化设计,有效减小了SHE的影响。该电路通过了4.5 kV人体模型ESD测试,相比国内外同类电路有较大提高,可以为深亚微米SOI工艺IC ESD防护设计提供参考。 展开更多
关键词 深亚微米 绝缘体上硅(SOI)工艺 全芯片 静电放电(ESD)防护 电源钳位 人体模型
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