The new type of embedded signal processing system based on the packet switched network is achieved. According to the application field and the-characteristics of signal processing system, the RapidIO protocol is used ...The new type of embedded signal processing system based on the packet switched network is achieved. According to the application field and the-characteristics of signal processing system, the RapidIO protocol is used to solve the high-speed interconnection of multi-digital signal processor （DSP）. Based on this protocol, a kind of crossbar switch module which is used to interconnect multi-DSP in the system is introduced. A route strategy, some flow control rules and error control rules, which adapt to different RapidIO network topology are also introduced. Crossbar switch performance is analyzed in detail by the probability module. By researching the technique of crossbar switch and analyzing the system performance, it has a significant meaning for building the general signal processing system.展开更多
基于减少8B/10B编码器占用的逻辑资源和保证该编码器误码率为0的目的,采用查表法和组合逻辑实现相结合的方法设计实现了符合嵌入式互连规范RapidIO协议的8B/10B编码器,通过伪随机二进制序列(Pseudo Random Binary Sequence,PRBS)检测方...基于减少8B/10B编码器占用的逻辑资源和保证该编码器误码率为0的目的,采用查表法和组合逻辑实现相结合的方法设计实现了符合嵌入式互连规范RapidIO协议的8B/10B编码器,通过伪随机二进制序列(Pseudo Random Binary Sequence,PRBS)检测方法对该编码器进行验证。FPGA综合结果表明,该设计占用的LUT为32,占用较少的逻辑资源。采用PRBS-7测试结果表明,该8B/10B编码电路误码率为0,表明了该8B/10B编码器传输信息的可靠性。展开更多
文摘The new type of embedded signal processing system based on the packet switched network is achieved. According to the application field and the-characteristics of signal processing system, the RapidIO protocol is used to solve the high-speed interconnection of multi-digital signal processor （DSP）. Based on this protocol, a kind of crossbar switch module which is used to interconnect multi-DSP in the system is introduced. A route strategy, some flow control rules and error control rules, which adapt to different RapidIO network topology are also introduced. Crossbar switch performance is analyzed in detail by the probability module. By researching the technique of crossbar switch and analyzing the system performance, it has a significant meaning for building the general signal processing system.
文摘基于减少8B/10B编码器占用的逻辑资源和保证该编码器误码率为0的目的,采用查表法和组合逻辑实现相结合的方法设计实现了符合嵌入式互连规范RapidIO协议的8B/10B编码器,通过伪随机二进制序列(Pseudo Random Binary Sequence,PRBS)检测方法对该编码器进行验证。FPGA综合结果表明,该设计占用的LUT为32,占用较少的逻辑资源。采用PRBS-7测试结果表明,该8B/10B编码电路误码率为0,表明了该8B/10B编码器传输信息的可靠性。
