摘要
RapidlO是一种点对点的基于包交换的交叉开关互联技术，以其高带宽、低延时及高可靠性为高性能的嵌入式系统内部互联通信提供了良好的解决方案。该文设计了串行RapidlO的性能测试平台，在此基础上测试了FPGA上实现的串行RapidlO接口的实际传输性能，最后根据试结果分析了影响传输效率的因素。
RapidlO is a point-to-point and packetet switched intercormection technology. With the characteristics of high bandwidth, low latency, reliability, it provides a favorable solution in the embedded interconnection. A performance test platform of serial RapidlO is de- signed in this paper, based on this, test the actual performance of serial RapidlO interfaces in FPGA. Finally, according to measurement re- sult, analysis the factors that impact the transfer efficiency.
作者
田泽
郭海英
TIAN Ze, GUO Hai-ying （School of Computer Science, Xi＇an Shiyou University, Xi＇an 710065, China）
出处
《电脑知识与技术》
2010年第10期8122-8124,共3页
Computer Knowledge and Technology
