We present a novel programming circuit used in our radiation-hardened field programmable gate array （FPGA） chip.This circuit provides the ability to write user-defined configuration data into an FPGA and then read i...We present a novel programming circuit used in our radiation-hardened field programmable gate array （FPGA） chip.This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back.The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain.It not only saves area but also provides more flexible configuration operations.By configuring the proposed partial configuration control register,our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented.The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well.Also,the radiation hardened by design programming point is introduced.This circuit has been implemented in a static random access memory（SRAM）-based FPGA fabricated by a 0.5μm partial-depletion silicon-on-insulator CMOS process.The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back.Moreover,the radiation test results indicate that the programming circuit has total dose tolerance of 1×10~5 rad（Si）,dose rate survivability of 1.5×10^（11） rad（Si）/s and neutron fluence immunity of 1×10^（14） n/cm^2.展开更多
A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute.The new logic cell （LC）,w...A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute.The new logic cell （LC）,with a multi-mode based on 3-input look-up-table（LUT）,increases logic density about 12%compared to a traditional 4-input LUT.The logic block（LB）,consisting of 2 LCs,can be used in two functional modes：LUT mode and distributed read access memory mode.The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource.The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs,112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming.The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly.Moreover,the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad（Si）,a dose rate survivability of 1.5×10^（11）rad（Si）/s and a neutron fluence immunity of 1×10^（14） n/cm^2.展开更多
文章对部分耗尽0.8μm SOI CMOS工艺源漏电阻产生影响的四个主要因素采用二水平全因子实验设计[1],分析结果表明在注入能量、剂量、束流和硅膜厚度因素中,硅膜厚度显著影响P+源漏电阻,当顶层硅膜厚度充分时,P+源漏电阻工艺窗口大。实验...文章对部分耗尽0.8μm SOI CMOS工艺源漏电阻产生影响的四个主要因素采用二水平全因子实验设计[1],分析结果表明在注入能量、剂量、束流和硅膜厚度因素中,硅膜厚度显著影响P+源漏电阻,当顶层硅膜厚度充分时,P+源漏电阻工艺窗口大。实验指出注入能量未处于合理的范围,导致源漏电阻工艺窗口不足,影响0.8μm SOI工艺成品率。通过实验优化后部分耗尽0.8μm SOI CMOS工艺P+源漏电阻达到小于200Ω/□,工艺能力显著提高到Ppk>2.01水平,充分满足部分耗尽0.8μm SOICMOS工艺P+源漏电阻需求。展开更多
Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact...Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact,respectively.By means of two-dimension(2D) device simulation and measuring junction breakdown of the drain and the body,the difference and limitation of the breakdown characteristics of devices with two technologies are analyzed and explained in details.Based on this,a method is proposed to improve off-state breakdown characteristics of PDSOI nMOS devices.展开更多
文摘We present a novel programming circuit used in our radiation-hardened field programmable gate array （FPGA） chip.This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back.The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain.It not only saves area but also provides more flexible configuration operations.By configuring the proposed partial configuration control register,our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented.The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well.Also,the radiation hardened by design programming point is introduced.This circuit has been implemented in a static random access memory（SRAM）-based FPGA fabricated by a 0.5μm partial-depletion silicon-on-insulator CMOS process.The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back.Moreover,the radiation test results indicate that the programming circuit has total dose tolerance of 1×10~5 rad（Si）,dose rate survivability of 1.5×10^（11） rad（Si）/s and neutron fluence immunity of 1×10^（14） n/cm^2.
文摘A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute.The new logic cell （LC）,with a multi-mode based on 3-input look-up-table（LUT）,increases logic density about 12%compared to a traditional 4-input LUT.The logic block（LB）,consisting of 2 LCs,can be used in two functional modes：LUT mode and distributed read access memory mode.The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource.The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs,112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming.The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly.Moreover,the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad（Si）,a dose rate survivability of 1.5×10^（11）rad（Si）/s and a neutron fluence immunity of 1×10^（14） n/cm^2.
文摘文章对部分耗尽0.8μm SOI CMOS工艺源漏电阻产生影响的四个主要因素采用二水平全因子实验设计[1],分析结果表明在注入能量、剂量、束流和硅膜厚度因素中,硅膜厚度显著影响P+源漏电阻,当顶层硅膜厚度充分时,P+源漏电阻工艺窗口大。实验指出注入能量未处于合理的范围,导致源漏电阻工艺窗口不足,影响0.8μm SOI工艺成品率。通过实验优化后部分耗尽0.8μm SOI CMOS工艺P+源漏电阻达到小于200Ω/□,工艺能力显著提高到Ppk>2.01水平,充分满足部分耗尽0.8μm SOICMOS工艺P+源漏电阻需求。
文摘Partial-depleted SOI(silicon on insulator) nMOS devices are fabricated with and without silicide technology,respectively.Off-state breakdown characteristics of these devices are presented with and without body contact,respectively.By means of two-dimension(2D) device simulation and measuring junction breakdown of the drain and the body,the difference and limitation of the breakdown characteristics of devices with two technologies are analyzed and explained in details.Based on this,a method is proposed to improve off-state breakdown characteristics of PDSOI nMOS devices.
