A full on-chip and area-efficient low-dropout linear regulator （LDO） is presented. By using the proposed adaptive frequency compensation （AFC） technique, full on-chip integration is achieved without compromising t...A full on-chip and area-efficient low-dropout linear regulator （LDO） is presented. By using the proposed adaptive frequency compensation （AFC） technique, full on-chip integration is achieved without compromising the LDO＇s stability in the full output current range. Meanwhile, the use of a compact pass transistor （the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique） has enabled the LDO to be very areaefficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 × 320/zm^2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.展开更多
A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, wh...A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.展开更多
An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage ...An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.展开更多
分析了LC压控振荡器(VCO)的相位噪声,提出了基于预稳压模块的低噪声低压差线性稳压器(LDO)结构,有效改善了电源噪声对LC VCO相位噪声的影响。设计了低噪声带隙基准电路和低噪声误差放大器,进一步优化LDO的输出噪声。通过调节反馈阻抗网...分析了LC压控振荡器(VCO)的相位噪声,提出了基于预稳压模块的低噪声低压差线性稳压器(LDO)结构,有效改善了电源噪声对LC VCO相位噪声的影响。设计了低噪声带隙基准电路和低噪声误差放大器,进一步优化LDO的输出噪声。通过调节反馈阻抗网络实现LDO输出电压可调,可以满足VCO的不同供电需求。通过改变滤波电容值,验证电源噪声对LC VCO的影响。采用0.35μm CMOS工艺进行了流片,测试结果表明,LDO在10 Hz^100 k Hz之间的输出均方根噪声电压为8.8μV,在-45~85℃温度范围内的温度系数约为43×10-6/℃;LC VCO输出频率范围为2.0~2.4 GHz,调谐范围为18.2%,相位噪声为-110.8 d Bc/Hz@100 k Hz,满足集成锁相环对LC VCO的噪声要求。展开更多
提出了一种新型的应用于低压差线性稳压器(LDO)的斜坡软启动电路,其采用两路斜坡使能信号以及一路斜坡基准信号,消除了电源上电时产生的浪涌电流。该斜坡软启动电路已应用于一款LDO中,并采用0.35μm CMOS工艺实现流片,其仅占LDO有效面积...提出了一种新型的应用于低压差线性稳压器(LDO)的斜坡软启动电路,其采用两路斜坡使能信号以及一路斜坡基准信号,消除了电源上电时产生的浪涌电流。该斜坡软启动电路已应用于一款LDO中,并采用0.35μm CMOS工艺实现流片,其仅占LDO有效面积的8.3%,消耗电流仅600 n A。仿真以及测试结果显示,采用该软启动电路之后,LDO的上电浪涌电流得到有效抑制。LDO在最差情况下的线性调整率为2.7 m V/V,负载调整率为0.064 m V/m A。展开更多
基金supported by Shanghai-Applied Material Research Development Fund(No.09700714100).
文摘A full on-chip and area-efficient low-dropout linear regulator （LDO） is presented. By using the proposed adaptive frequency compensation （AFC） technique, full on-chip integration is achieved without compromising the LDO＇s stability in the full output current range. Meanwhile, the use of a compact pass transistor （the compact pass transistor serves as the gain fast roll-off output stage in the AFC technique） has enabled the LDO to be very areaefficient. The proposed LDO is implemented in standard 0.35 μm CMOS technology and occupies an active area as small as 220 × 320/zm^2, which is a reduction to 58% compared to state-of-the-art designs using technologies with the same feature size. Measurement results show that the LDO can deliver 0-60 mA output current with 54 μA quiescent current consumption and the regulated output voltage is 1.8 V with an input voltage range from 2 to 3.3 V.
文摘A capacitor-free CMOS low-dropout （LDO） regulator for system-on-chip （SoC） applications is presented. By adopting AC-boosting and active-feedback frequency compensation （ACB-AFFC）, the proposed LDO regulator, which is independent of an off-chip capacitor, provides high closed-loop stability. Moreover, a slew rate enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high. The LDO regulator is designed and fabricated in a 0.6 μm CMOS process. The active silicon area is only 770 × 472 μm2. Experimental results show that the total error of the output voltage due to line variation is less than ±0.197%. The load regulation is only 0.35 mV/mA when the load current changes from 0 to 100 mA.
文摘An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.
文摘分析了LC压控振荡器(VCO)的相位噪声,提出了基于预稳压模块的低噪声低压差线性稳压器(LDO)结构,有效改善了电源噪声对LC VCO相位噪声的影响。设计了低噪声带隙基准电路和低噪声误差放大器,进一步优化LDO的输出噪声。通过调节反馈阻抗网络实现LDO输出电压可调,可以满足VCO的不同供电需求。通过改变滤波电容值,验证电源噪声对LC VCO的影响。采用0.35μm CMOS工艺进行了流片,测试结果表明,LDO在10 Hz^100 k Hz之间的输出均方根噪声电压为8.8μV,在-45~85℃温度范围内的温度系数约为43×10-6/℃;LC VCO输出频率范围为2.0~2.4 GHz,调谐范围为18.2%,相位噪声为-110.8 d Bc/Hz@100 k Hz,满足集成锁相环对LC VCO的噪声要求。
文摘提出了一种新型的应用于低压差线性稳压器(LDO)的斜坡软启动电路,其采用两路斜坡使能信号以及一路斜坡基准信号,消除了电源上电时产生的浪涌电流。该斜坡软启动电路已应用于一款LDO中,并采用0.35μm CMOS工艺实现流片,其仅占LDO有效面积的8.3%,消耗电流仅600 n A。仿真以及测试结果显示,采用该软启动电路之后,LDO的上电浪涌电流得到有效抑制。LDO在最差情况下的线性调整率为2.7 m V/V,负载调整率为0.064 m V/m A。
