摘要
提出了一种全片内集成的低噪声CMOS低压差线性稳压器(LDO).首先建立传统LDO的噪声模型,分析了关键噪声来源并提出采用低噪声参考电压源来降低LDO输出噪声的方法.其次,提出一种带数字校正的基于阈值电压的低噪声参考电压源,用TSMC 0.18μm RF CMOS工艺设计并完成了为低相位噪声锁相环(PLL)电路供电的全片内集成低噪声LDO的流片和测试.该LDO被集成于高性能射频接收器芯片中.仿真结果表明,LDO的输出噪声低于26nV/Hz^(1/2)@100kHz,14nV/Hz^(1/2)@1MHz,电源抑制比达到-40dB@1MHz,全频率范围内低于-34dB.测试结果表明采用该低噪声LDO的PLL电路与采用传统LDO的PLL电路相比,其相位噪声降低6dBc@1kHz,低2dBc@200kHz.
A fully on-chip low-dropout linear regulator （LDO） with ultra low noise is presented. This regulator uses a Vt/R based voltage reference rather than a commonly used bandgap reference to minimize the noise introduced by the reference voltage. The Vt/R based voltage reference employs a digital calibration schema to increase the accuracy of the output voltage. This fully on-chip LDO is designed in a TSMC 0.18rtm RF CMOS process for the power supply of a low phase noise phase lock loop （PLL） with 10mA of DC current consumption. The simulation results indicate that the total output noise of the LDO is 26nV/^-Hz@ 100kHz and 14nV/~＇-H-z@ 1MHz, and the power supply reject ratio is - 40dB@ 1MHz and less than - 34dB in all frequency bands. The test results show that the phase noise of the PLL using this LDO is 6dBc@lkHz less and 2dBc@200kHz less than using conventional LDO.
